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Commit 6d202fbf authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Adding CoreTech sa8195 DT Changes to Mainline 5.4"

parents 8e63c2dc e598c121

qcom/sa8195-qupv3.dtsi

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qcom/sa8195-ssc-qupv3.dtsi

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#include <dt-bindings/interconnect/qcom,scshrike.h>



&soc {

	/* QUPv3 SSC Instance */

	qupv3_3: qcom,qupv3_3_geni_se@26c0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0x26c0000 0x6000>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-bus-ids =

			<MASTER_SENSORS_AHB SLAVE_EBI1>;

		iommus = <&apps_smmu 0x4e3 0x0>;

		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;

		qcom,iommu-dma = "fastmap";

		status = "disabled";

	};



	/* I2C*/

	qupv3_se20_i2c: i2c@2680000 {

		compatible = "qcom,i2c-geni";

		reg = <0x2680000 0x4000>;

		interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&scc SCC_QUPV3_SE0_CLK>,

			<&scc SCC_QUPV3_M_HCLK_CLK>,

			<&scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se20_i2c_active>;

		pinctrl-1 = <&qupv3_se20_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_3>;

		status = "disabled";

	};



	qupv3_se21_i2c: i2c@2684000 {

		compatible = "qcom,i2c-geni";

		reg = <0x2684000 0x4000>;

		interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&scc SCC_QUPV3_SE1_CLK>,

			<&scc SCC_QUPV3_M_HCLK_CLK>,

			<&scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se21_i2c_active>;

		pinctrl-1 = <&qupv3_se21_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_3>;

		status = "disabled";

	};



	qupv3_se22_i2c: i2c@2688000 {

		compatible = "qcom,i2c-geni";

		reg = <0x2688000 0x4000>;

		interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&scc SCC_QUPV3_SE2_CLK>,

			<&scc SCC_QUPV3_M_HCLK_CLK>,

			<&scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se22_i2c_active>;

		pinctrl-1 = <&qupv3_se22_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_3>;

		status = "disabled";

	};



	/* SPI */

	qupv3_se21_spi: spi@2684000 {

		compatible = "qcom,spi-geni";

		reg = <0x2684000 0x4000>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&scc SCC_QUPV3_SE1_CLK>,

			<&scc SCC_QUPV3_M_HCLK_CLK>,

			<&scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se21_spi_active>;

		pinctrl-1 = <&qupv3_se21_spi_sleep>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_3>;

		qcom,disable-dma;

		status = "disabled";

	};



	qupv3_se22_spi: spi@2688000 {

		compatible = "qcom,spi-geni";

		reg = <0x2688000 0x4000>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&scc SCC_QUPV3_SE2_CLK>,

			<&scc SCC_QUPV3_M_HCLK_CLK>,

			<&scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se22_spi_active>;

		pinctrl-1 = <&qupv3_se22_spi_sleep>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_3>;

		qcom,disable-dma;

		status = "disabled";

	};

};

qcom/sa8195-usb.dtsi

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#include <dt-bindings/clock/qcom,gcc-scshrike.h>



&soc {

	/* Primary USB port related controller */

	usb0: ssusb@a600000 {

		compatible = "qcom,dwc-usb3-msm";

		reg = <0x0a600000 0x100000>;

		reg-names = "core_base";



		iommus = <&apps_smmu 0x140 0x0>;

		qcom,iommu-dma = "atomic";

		qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;



		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		dma-ranges;



		interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,

				<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 8 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",

				"ss_phy_irq", "dm_hs_phy_irq";

		qcom,use-pdc-interrupts;



		USB3_GDSC-supply = <&usb30_prim_gdsc>;

		clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,

			<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,

			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,

			<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,

			<&gcc GCC_USB30_PRIM_SLEEP_CLK>,

			<&rpmhcc RPMH_CXO_CLK>;

		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",

					"utmi_clk", "sleep_clk", "xo";



		resets = <&gcc GCC_USB30_PRIM_BCR>;

		reset-names = "core_reset";



		qcom,core-clk-rate = <200000000>;

		qcom,core-clk-rate-hs = <66666667>;

		qcom,dwc-usb3-msm-tx-fifo-size = <27696>;



		qcom,ignore-wakeup-src-in-hostmode;



		interconnect-names = "usb-ddr", "ddr-usb";

		interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,

				<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;



		dwc3@a600000 {

			compatible = "snps,dwc3";

			reg = <0x0a600000 0xcd00>;

			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;

			usb-phy = <&usb2_phy0>, <&usb_nop_phy>;

			linux,sysdev_is_parent;

			snps,disable-clk-gating;

			snps,has-lpm-erratum;

			snps,hird-threshold = /bits/ 8 <0x0>;

			snps,is-utmi-l1-suspend;

			maximum-speed = "high-speed";

			dr_mode = "otg";

		};



		qcom,usbbam@a704000 {

			compatible = "qcom,usb-bam-msm";

			reg = <0xa704000 0x17000>;

			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;



			qcom,usb-bam-fifo-baseaddr = <0x146bb000>;

			qcom,usb-bam-num-pipes = <4>;

			qcom,disable-clk-gating;

			qcom,usb-bam-override-threshold = <0x4001>;

			qcom,usb-bam-max-mbps-highspeed = <400>;

			qcom,usb-bam-max-mbps-superspeed = <3600>;

			qcom,reset-bam-on-connect;



			qcom,pipe0 {

				label = "ssusb-qdss-in-0";

				qcom,usb-bam-mem-type = <2>;

				qcom,dir = <1>;

				qcom,pipe-num = <0>;

				qcom,peer-bam = <0>;

				qcom,peer-bam-physical-address = <0x6064000>;

				qcom,src-bam-pipe-index = <0>;

				qcom,dst-bam-pipe-index = <0>;

				qcom,data-fifo-offset = <0x0>;

				qcom,data-fifo-size = <0x1800>;

				qcom,descriptor-fifo-offset = <0x1800>;

				qcom,descriptor-fifo-size = <0x800>;

			};

		};

	};



	/* Primary USB port related High Speed PHY */

	usb2_phy0: hsphy@88e2000 {

		compatible = "qcom,usb-hsphy-snps-femto";

		reg = <0x88e2000 0x110>,

		    <0x007801f8 0x4>;

		reg-names = "hsusb_phy_base",

			"phy_rcal_reg";



		vdd-supply = <&pm8150_2_l5>;

		vdda18-supply = <&pm8150_1_l12>;

		vdda33-supply = <&pm8150_2_l16>;

		qcom,vdd-voltage-level = <0 880000 880000>;



		clocks = <&rpmhcc RPMH_CXO_CLK>;

		clock-names = "ref_clk_src";



		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

		reset-names = "phy_reset";

		qcom,param-override-seq = <0x43 0x70>;

		qcom,rcal-mask = <0x1e00000>;

	};



	usb_nop_phy: usb_nop_phy {

		compatible = "usb-nop-xceiv";

	};



	/* Secondary USB port related controller */

	usb1: ssusb@a800000 {

		compatible = "qcom,dwc-usb3-msm";

		reg = <0x0a800000 0x100000>;

		reg-names = "core_base";



		iommus = <&apps_smmu 0x160 0x0>;

		qcom,iommu-dma = "atomic";

		qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;



		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		dma-ranges;



		interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>,

				<&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 40 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 10 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",

				"ss_phy_irq", "dm_hs_phy_irq";

		qcom,use-pdc-interrupts;



		qcom,default-mode-host;

		qcom,ignore-wakeup-src-in-hostmode;



		USB3_GDSC-supply = <&usb30_sec_gdsc>;

		clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,

			<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,

			<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,

			<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,

			<&gcc GCC_USB30_SEC_SLEEP_CLK>,

			<&rpmhcc RPMH_CXO_CLK>;

		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",

					"utmi_clk", "sleep_clk", "xo";



		resets = <&gcc GCC_USB30_SEC_BCR>;

		reset-names = "core_reset";



		qcom,core-clk-rate = <200000000>;

		qcom,core-clk-rate-hs = <66666667>;

		qcom,dwc-usb3-msm-tx-fifo-size = <27696>;



		interconnect-names = "usb-ddr", "ddr-usb";

		interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>,

				<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>;



		dwc3@a800000 {

			compatible = "snps,dwc3";

			reg = <0x0a800000 0xcd00>;

			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			usb-phy = <&usb2_phy1>, <&usb_nop_phy>;

			linux,sysdev_is_parent;

			snps,disable-clk-gating;

			snps,has-lpm-erratum;

			snps,hird-threshold = /bits/ 8 <0x0>;

			snps,is-utmi-l1-suspend;

			maximum-speed = "high-speed";

			dr_mode = "otg";

		};

	};



	/* Secondary USB port related High Speed PHY */

	usb2_phy1: hsphy@88e3000 {

		compatible = "qcom,usb-hsphy-snps-femto";

		reg = <0x88e3000 0x110>,

		   <0x007801f8 0x4>;

		reg-names = "hsusb_phy_base",

			"phy_rcal_reg";



		vdd-supply = <&pm8150_2_l5>;

		vdda18-supply = <&pm8150_1_l12>;

		vdda33-supply = <&pm8150_2_l16>;

		qcom,vdd-voltage-level = <0 880000 880000>;



		clocks = <&rpmhcc RPMH_CXO_CLK>;

		clock-names = "ref_clk_src";



		resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;

		reset-names = "phy_reset";

		qcom,param-override-seq = <0x43 0x70>;

		qcom,rcal-mask = <0x1e00000>;

	};

};

qcom/sa8195p-adp-common.dtsi

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#include <dt-bindings/gpio/gpio.h>



&qupv3_id_1 {

&qupv3_3 {

	status = "ok";

};



&qupv3_se12_2uart {

	status = "ok";

};



&sdhc_2 {

	vdd-supply = <&pm8195_1_l10>;

	qcom,vdd-voltage-level = <2950000 2960000>;

	qcom,vdd-current-level = <200 800000>;



	vdd-io-supply = <&pm8195_1_l2>;

	qcom,vdd-io-voltage-level = <1808000 2960000>;

	qcom,vdd-io-current-level = <200 22000>;



	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&sdc2_on>;

	pinctrl-1 = <&sdc2_off>;



	cd-gpios = <&pm8195_1_gpios 4 GPIO_ACTIVE_LOW>;



	status = "ok";

};

qcom/sa8195p-pcie.dtsi

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