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Commit 6d04630e authored by Charan Teja Kalla's avatar Charan Teja Kalla
Browse files

ARM: dts: msm: update interconnect and global interuupts on yupik 

This change does the following:

1) Remove kgsl smmu interconnect node. For TCU config register access we
shouldn't required DDR path votes.  KGSL smmu already votes for clock
and regulator.

2) Remove the tcu_comb_irpt_ns for both apps and kgsl smmu as the
interrupt is OR of context interrupts, TBU perf interrupts and global
fault interrupts. This interrupt is not really required and registering
for the same can showup as the global faults in EL1.

Change-Id: I4de4a866d936f1f7f053479dc00c72c46e84d80d
parent 5abae268

qcom/msm-arm-smmu-yupik.dtsi

+2 −6
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ 
		qcom,skip-init;

		qcom,use-3-lvl-tables;

		qcom,split-tables;

		#global-interrupts = <2>;

		#global-interrupts = <1>;

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;
@@ -33,10 +33,7 @@ 
			"gpu_cc_hub_cx_int_clk",

			"gpu_cc_hub_aon_clk";



		interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>;



		interrupts =	<GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
@@ -77,13 +74,12 @@ 
		#iommu-cells = <2>;

		qcom,skip-init;

		qcom,use-3-lvl-tables;

		#global-interrupts = <2>;

		#global-interrupts = <1>;

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		dma-coherent;

		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,