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Commit 6c710cb3 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Make OOB timeouts easier to debug"

parents 42372239 85de6535

drivers/gpu/msm/adreno.c

+6 −11
Original line number Diff line number Diff line
@@ -1860,9 +1860,8 @@ static void adreno_set_active_ctxs_null(struct adreno_device *adreno_dev) 
			kgsl_context_put(&(rb->drawctxt_active->base));

		rb->drawctxt_active = NULL;



		kgsl_sharedmem_writel(KGSL_DEVICE(adreno_dev),

			rb->pagetable_desc, PT_INFO_OFFSET(current_rb_ptname),

			0);

		kgsl_sharedmem_writel(rb->pagetable_desc,

			PT_INFO_OFFSET(current_rb_ptname), 0);

	}

}
@@ -1877,8 +1876,7 @@ static int adreno_first_open(struct kgsl_device *device) 
	 */

	atomic_inc(&device->active_cnt);



	kgsl_sharedmem_set(device, device->memstore, 0, 0,

		device->memstore->size);

	memset(device->memstore->hostptr, 0, device->memstore->size);



	ret = adreno_init(device);

	if (ret)
@@ -2120,7 +2118,7 @@ static int _adreno_start(struct adreno_device *adreno_dev) 
	/* Clear FSR here in case it is set from a previous pagefault */

	kgsl_mmu_clear_fsr(&device->mmu);



	status = adreno_ringbuffer_start(adreno_dev);

	status = gpudev->rb_start(adreno_dev);

	if (status)

		goto error_oob_clear;
@@ -2782,12 +2780,9 @@ static int adreno_soft_reset(struct kgsl_device *device) 


	/* stop all ringbuffers to cancel RB events */

	adreno_ringbuffer_stop(adreno_dev);

	/*

	 * If we have offsets for the jump tables we can try to do a warm start,

	 * otherwise do a full ringbuffer restart

	 */



	ret = adreno_ringbuffer_start(adreno_dev);

	/* Start the ringbuffer(s) again */

	ret = gpudev->rb_start(adreno_dev);

	if (ret == 0) {

		device->reset_counter++;

		set_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv);

drivers/gpu/msm/adreno.h

+4 −9
Original line number Diff line number Diff line
@@ -1464,29 +1464,24 @@ static inline bool adreno_support_64bit(struct adreno_device *adreno_dev) 
static inline void adreno_ringbuffer_set_global(

		struct adreno_device *adreno_dev, int name)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);



	kgsl_sharedmem_writel(device,

		adreno_dev->ringbuffers[0].pagetable_desc,

	kgsl_sharedmem_writel(adreno_dev->ringbuffers[0].pagetable_desc,

		PT_INFO_OFFSET(current_global_ptname), name);

}



static inline void adreno_ringbuffer_set_pagetable(struct adreno_ringbuffer *rb,

		struct kgsl_pagetable *pt)

{

	struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb);

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	unsigned long flags;



	spin_lock_irqsave(&rb->preempt_lock, flags);



	kgsl_sharedmem_writel(device, rb->pagetable_desc,

	kgsl_sharedmem_writel(rb->pagetable_desc,

		PT_INFO_OFFSET(current_rb_ptname), pt->name);



	kgsl_sharedmem_writeq(device, rb->pagetable_desc,

	kgsl_sharedmem_writeq(rb->pagetable_desc,

		PT_INFO_OFFSET(ttbr0), kgsl_mmu_pagetable_get_ttbr0(pt));



	kgsl_sharedmem_writel(device, rb->pagetable_desc,

	kgsl_sharedmem_writel(rb->pagetable_desc,

		PT_INFO_OFFSET(contextidr),

		kgsl_mmu_pagetable_get_contextidr(pt));

drivers/gpu/msm/adreno_a3xx.c

+9 −4
Original line number Diff line number Diff line
@@ -602,8 +602,14 @@ static void a3xx_microcode_load(struct adreno_device *adreno_dev); 


static int a3xx_rb_start(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct adreno_ringbuffer *rb = ADRENO_CURRENT_RINGBUFFER(adreno_dev);



	memset(rb->buffer_desc->hostptr, 0xaa, KGSL_RB_SIZE);

	rb->wptr = 0;

	rb->_wptr = 0;

	rb->wptr_preempt_end = ~0;



	/*

	 * The size of the ringbuffer in the hardware is the log2

	 * representation of the size in quadwords (sizedwords / 2).
@@ -611,17 +617,16 @@ static int a3xx_rb_start(struct adreno_device *adreno_dev) 
	 * in certain circumstances.

	 */



	adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_CNTL,

	kgsl_regwrite(device, A3XX_CP_RB_CNTL,

		(ilog2(KGSL_RB_DWORDS >> 1) & 0x3F) |

		(1 << 27));



	adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_BASE,

			rb->buffer_desc->gpuaddr);

	kgsl_regwrite(device, A3XX_CP_RB_BASE, rb->buffer_desc->gpuaddr);



	a3xx_microcode_load(adreno_dev);



	/* clear ME_HALT to start micro engine */

	adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_CNTL, 0);

	kgsl_regwrite(device, A3XX_CP_ME_CNTL, 0);



	return a3xx_send_me_init(adreno_dev, rb);

}

drivers/gpu/msm/adreno_a3xx_snapshot.c

+14 −4
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2012-2017,2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2012-2017,2019-2020, The Linux Foundation. All rights reserved.

 */



#include <linux/io.h>
@@ -353,7 +353,17 @@ void a3xx_snapshot(struct adreno_device *adreno_dev, 
	unsigned int reg, val;



	/* Disable Clock gating temporarily for the debug bus to work */

	adreno_writereg(adreno_dev, ADRENO_REG_RBBM_CLOCK_CTL, 0x00);

	kgsl_regwrite(device, A3XX_RBBM_CLOCK_CTL, 0x0);



	/* Save some CP information that the generic snapshot uses */

	kgsl_regread(device, A3XX_CP_IB1_BASE, &reg);

	snapshot->ib1base = (u64) reg;



	kgsl_regread(device, A3XX_CP_IB2_BASE, &reg);

	snapshot->ib2base = (u64) reg;



	kgsl_regread(device, A3XX_CP_IB1_BUFSZ, &snapshot->ib1size);

	kgsl_regread(device, A3XX_CP_IB2_BUFSZ, &snapshot->ib2size);



	SNAPSHOT_REGISTERS(device, snapshot, a3xx_registers);
@@ -393,9 +403,9 @@ void a3xx_snapshot(struct adreno_device *adreno_dev, 
	 * care about the contents of the CP anymore.

	 */



	adreno_readreg(adreno_dev, ADRENO_REG_CP_ME_CNTL, &reg);

	kgsl_regread(device, A3XX_CP_ME_CNTL, &reg);

	reg |= (1 << 27) | (1 << 28);

	adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_CNTL, reg);

	kgsl_regwrite(device, A3XX_CP_ME_CNTL, reg);



	kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG,

		snapshot, a3xx_snapshot_cp_pfp_ram, NULL);

drivers/gpu/msm/adreno_a5xx.c

+25 −18
Original line number Diff line number Diff line
@@ -1813,15 +1813,28 @@ static int a5xx_send_me_init(struct adreno_device *adreno_dev, 
 */

static int a5xx_rb_start(struct adreno_device *adreno_dev)

{

	struct adreno_ringbuffer *rb = ADRENO_CURRENT_RINGBUFFER(adreno_dev);

	struct kgsl_device *device = &adreno_dev->dev;

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct adreno_ringbuffer *rb;

	uint64_t addr;

	int ret;

	int ret, i;



	/* Clear all the ringbuffers */

	FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {

		memset(rb->buffer_desc->hostptr, 0xaa, KGSL_RB_SIZE);

		kgsl_sharedmem_writel(device->scratch,

			SCRATCH_RPTR_OFFSET(rb->id), 0);



		rb->wptr = 0;

		rb->_wptr = 0;

		rb->wptr_preempt_end = ~0;

	}



	/* Set up the current ringbuffer */

	rb = ADRENO_CURRENT_RINGBUFFER(adreno_dev);

	addr = SCRATCH_RPTR_GPU_ADDR(device, rb->id);



	adreno_writereg64(adreno_dev, ADRENO_REG_CP_RB_RPTR_ADDR_LO,

			ADRENO_REG_CP_RB_RPTR_ADDR_HI, addr);

	kgsl_regwrite(device, A5XX_CP_RB_RPTR_ADDR_LO, lower_32_bits(addr));

	kgsl_regwrite(device, A5XX_CP_RB_RPTR_ADDR_HI, upper_32_bits(addr));



	/*

	 * The size of the ringbuffer in the hardware is the log2
@@ -1830,18 +1843,21 @@ static int a5xx_rb_start(struct adreno_device *adreno_dev) 
	 * in certain circumstances.

	 */



	adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_CNTL,

	kgsl_regwrite(device, A5XX_CP_RB_CNTL,

		A5XX_CP_RB_CNTL_DEFAULT);



	adreno_writereg64(adreno_dev, ADRENO_REG_CP_RB_BASE,

			ADRENO_REG_CP_RB_BASE_HI, rb->buffer_desc->gpuaddr);

	kgsl_regwrite(device, A5XX_CP_RB_BASE,

		lower_32_bits(rb->buffer_desc->gpuaddr));

	kgsl_regwrite(device, A5XX_CP_RB_BASE_HI,

		upper_32_bits(rb->buffer_desc->gpuaddr));



	ret = a5xx_microcode_load(adreno_dev);

	if (ret)

		return ret;



	/* clear ME_HALT to start micro engine */

	adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_CNTL, 0);



	kgsl_regwrite(device, A5XX_CP_ME_CNTL, 0);



	ret = a5xx_send_me_init(adreno_dev, rb);

	if (ret)
@@ -2314,13 +2330,6 @@ static struct adreno_perfcounters a5xx_perfcounters = { 
	ARRAY_SIZE(a5xx_perfcounter_groups),

};



static struct adreno_ft_perf_counters a5xx_ft_perf_counters[] = {

	{KGSL_PERFCOUNTER_GROUP_SP, A5XX_SP_ALU_ACTIVE_CYCLES},

	{KGSL_PERFCOUNTER_GROUP_SP, A5XX_SP0_ICL1_MISSES},

	{KGSL_PERFCOUNTER_GROUP_SP, A5XX_SP_FS_CFLOW_INSTRUCTIONS},

	{KGSL_PERFCOUNTER_GROUP_TSE, A5XX_TSE_INPUT_PRIM_NUM},

};



/* Register offset defines for A5XX, in order of enum adreno_regs */

static unsigned int a5xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE, A5XX_CP_RB_BASE),
@@ -2958,8 +2967,6 @@ static struct adreno_coresight a5xx_coresight = { 


struct adreno_gpudev adreno_a5xx_gpudev = {

	.reg_offsets = a5xx_register_offsets,

	.ft_perf_counters = a5xx_ft_perf_counters,

	.ft_perf_counters_count = ARRAY_SIZE(a5xx_ft_perf_counters),

#ifdef CONFIG_QCOM_KGSL_CORESIGHT

	.coresight = {&a5xx_coresight},

#endif