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Commit 6c587584 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc: slightly improve cache helpers 



Cache instructions (dcbz, dcbi, dcbf and dcbst) take two registers
that are summed to obtain the target address. Using 'Z' constraint
and '%y0' argument gives GCC the opportunity to use both registers
instead of only one with the second being forced to 0.

Suggested-by: default avatarSegher Boessenkool <segher@kernel.crashing.org>
Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent ac25ba68

arch/powerpc/include/asm/cache.h

+4 −4
Original line number Diff line number Diff line
@@ -85,22 +85,22 @@ extern void _set_L3CR(unsigned long); 


static inline void dcbz(void *addr)

{

	__asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory");

	__asm__ __volatile__ ("dcbz %y0" : : "Z"(*(u8 *)addr) : "memory");

}



static inline void dcbi(void *addr)

{

	__asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory");

	__asm__ __volatile__ ("dcbi %y0" : : "Z"(*(u8 *)addr) : "memory");

}



static inline void dcbf(void *addr)

{

	__asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory");

	__asm__ __volatile__ ("dcbf %y0" : : "Z"(*(u8 *)addr) : "memory");

}



static inline void dcbst(void *addr)

{

	__asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory");

	__asm__ __volatile__ ("dcbst %y0" : : "Z"(*(u8 *)addr) : "memory");

}

#endif /* !__ASSEMBLY__ */

#endif /* __KERNEL__ */