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Commit 6c50c1ed authored by Yangbo Lu's avatar Yangbo Lu Committed by David S. Miller
Browse files

ptp_qoriq: move some definitions to header file 



This patch is to move some definitions in ptp_qoriq.c
to the header file.

Signed-off-by: default avatarYangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ceefc71d

drivers/ptp/ptp_qoriq.c

+1 −131
Original line number Diff line number Diff line
@@ -28,139 +28,9 @@ 
#include <linux/of.h>

#include <linux/of_platform.h>

#include <linux/timex.h>

#include <linux/io.h>

#include <linux/slab.h>



#include <linux/ptp_clock_kernel.h>



/*

 * qoriq ptp registers

 * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010

 */

struct qoriq_ptp_registers {

	u32 tmr_ctrl;     /* Timer control register */

	u32 tmr_tevent;   /* Timestamp event register */

	u32 tmr_temask;   /* Timer event mask register */

	u32 tmr_pevent;   /* Timestamp event register */

	u32 tmr_pemask;   /* Timer event mask register */

	u32 tmr_stat;     /* Timestamp status register */

	u32 tmr_cnt_h;    /* Timer counter high register */

	u32 tmr_cnt_l;    /* Timer counter low register */

	u32 tmr_add;      /* Timer drift compensation addend register */

	u32 tmr_acc;      /* Timer accumulator register */

	u32 tmr_prsc;     /* Timer prescale */

	u8  res1[4];

	u32 tmroff_h;     /* Timer offset high */

	u32 tmroff_l;     /* Timer offset low */

	u8  res2[8];

	u32 tmr_alarm1_h; /* Timer alarm 1 high register */

	u32 tmr_alarm1_l; /* Timer alarm 1 high register */

	u32 tmr_alarm2_h; /* Timer alarm 2 high register */

	u32 tmr_alarm2_l; /* Timer alarm 2 high register */

	u8  res3[48];

	u32 tmr_fiper1;   /* Timer fixed period interval */

	u32 tmr_fiper2;   /* Timer fixed period interval */

	u32 tmr_fiper3;   /* Timer fixed period interval */

	u8  res4[20];

	u32 tmr_etts1_h;  /* Timestamp of general purpose external trigger */

	u32 tmr_etts1_l;  /* Timestamp of general purpose external trigger */

	u32 tmr_etts2_h;  /* Timestamp of general purpose external trigger */

	u32 tmr_etts2_l;  /* Timestamp of general purpose external trigger */

};



/* Bit definitions for the TMR_CTRL register */

#define ALM1P                 (1<<31) /* Alarm1 output polarity */

#define ALM2P                 (1<<30) /* Alarm2 output polarity */

#define FIPERST               (1<<28) /* FIPER start indication */

#define PP1L                  (1<<27) /* Fiper1 pulse loopback mode enabled. */

#define PP2L                  (1<<26) /* Fiper2 pulse loopback mode enabled. */

#define TCLK_PERIOD_SHIFT     (16) /* 1588 timer reference clock period. */

#define TCLK_PERIOD_MASK      (0x3ff)

#define RTPE                  (1<<15) /* Record Tx Timestamp to PAL Enable. */

#define FRD                   (1<<14) /* FIPER Realignment Disable */

#define ESFDP                 (1<<11) /* External Tx/Rx SFD Polarity. */

#define ESFDE                 (1<<10) /* External Tx/Rx SFD Enable. */

#define ETEP2                 (1<<9) /* External trigger 2 edge polarity */

#define ETEP1                 (1<<8) /* External trigger 1 edge polarity */

#define COPH                  (1<<7) /* Generated clock output phase. */

#define CIPH                  (1<<6) /* External oscillator input clock phase */

#define TMSR                  (1<<5) /* Timer soft reset. */

#define BYP                   (1<<3) /* Bypass drift compensated clock */

#define TE                    (1<<2) /* 1588 timer enable. */

#define CKSEL_SHIFT           (0)    /* 1588 Timer reference clock source */

#define CKSEL_MASK            (0x3)



/* Bit definitions for the TMR_TEVENT register */

#define ETS2                  (1<<25) /* External trigger 2 timestamp sampled */

#define ETS1                  (1<<24) /* External trigger 1 timestamp sampled */

#define ALM2                  (1<<17) /* Current time = alarm time register 2 */

#define ALM1                  (1<<16) /* Current time = alarm time register 1 */

#define PP1                   (1<<7)  /* periodic pulse generated on FIPER1 */

#define PP2                   (1<<6)  /* periodic pulse generated on FIPER2 */

#define PP3                   (1<<5)  /* periodic pulse generated on FIPER3 */



/* Bit definitions for the TMR_TEMASK register */

#define ETS2EN                (1<<25) /* External trigger 2 timestamp enable */

#define ETS1EN                (1<<24) /* External trigger 1 timestamp enable */

#define ALM2EN                (1<<17) /* Timer ALM2 event enable */

#define ALM1EN                (1<<16) /* Timer ALM1 event enable */

#define PP1EN                 (1<<7) /* Periodic pulse event 1 enable */

#define PP2EN                 (1<<6) /* Periodic pulse event 2 enable */



/* Bit definitions for the TMR_PEVENT register */

#define TXP2                  (1<<9) /* PTP transmitted timestamp im TXTS2 */

#define TXP1                  (1<<8) /* PTP transmitted timestamp in TXTS1 */

#define RXP                   (1<<0) /* PTP frame has been received */



/* Bit definitions for the TMR_PEMASK register */

#define TXP2EN                (1<<9) /* Transmit PTP packet event 2 enable */

#define TXP1EN                (1<<8) /* Transmit PTP packet event 1 enable */

#define RXPEN                 (1<<0) /* Receive PTP packet event enable */



/* Bit definitions for the TMR_STAT register */

#define STAT_VEC_SHIFT        (0) /* Timer general purpose status vector */

#define STAT_VEC_MASK         (0x3f)



/* Bit definitions for the TMR_PRSC register */

#define PRSC_OCK_SHIFT        (0) /* Output clock division/prescale factor. */

#define PRSC_OCK_MASK         (0xffff)





#define DRIVER		"ptp_qoriq"

#define DEFAULT_CKSEL	1

#define N_EXT_TS	2

#define REG_SIZE	sizeof(struct qoriq_ptp_registers)



struct qoriq_ptp {

	struct qoriq_ptp_registers __iomem *regs;

	spinlock_t lock; /* protects regs */

	struct ptp_clock *clock;

	struct ptp_clock_info caps;

	struct resource *rsrc;

	int irq;

	int phc_index;

	u64 alarm_interval; /* for periodic alarm */

	u64 alarm_value;

	u32 tclk_period;  /* nanoseconds */

	u32 tmr_prsc;

	u32 tmr_add;

	u32 cksel;

	u32 tmr_fiper1;

	u32 tmr_fiper2;

};



static inline u32 qoriq_read(unsigned __iomem *addr)

{

	u32 val;



	val = ioread32be(addr);

	return val;

}



static inline void qoriq_write(unsigned __iomem *addr, u32 val)

{

	iowrite32be(val, addr);

}

#include <linux/fsl/ptp_qoriq.h>



/*

 * Register access functions

include/linux/fsl/ptp_qoriq.h

0 → 100644
+141 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2010 OMICRON electronics GmbH

 * Copyright 2018 NXP

 */

#ifndef __PTP_QORIQ_H__

#define __PTP_QORIQ_H__



#include <linux/io.h>

#include <linux/ptp_clock_kernel.h>



/*

 * qoriq ptp registers

 * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010

 */

struct qoriq_ptp_registers {

	u32 tmr_ctrl;     /* Timer control register */

	u32 tmr_tevent;   /* Timestamp event register */

	u32 tmr_temask;   /* Timer event mask register */

	u32 tmr_pevent;   /* Timestamp event register */

	u32 tmr_pemask;   /* Timer event mask register */

	u32 tmr_stat;     /* Timestamp status register */

	u32 tmr_cnt_h;    /* Timer counter high register */

	u32 tmr_cnt_l;    /* Timer counter low register */

	u32 tmr_add;      /* Timer drift compensation addend register */

	u32 tmr_acc;      /* Timer accumulator register */

	u32 tmr_prsc;     /* Timer prescale */

	u8  res1[4];

	u32 tmroff_h;     /* Timer offset high */

	u32 tmroff_l;     /* Timer offset low */

	u8  res2[8];

	u32 tmr_alarm1_h; /* Timer alarm 1 high register */

	u32 tmr_alarm1_l; /* Timer alarm 1 high register */

	u32 tmr_alarm2_h; /* Timer alarm 2 high register */

	u32 tmr_alarm2_l; /* Timer alarm 2 high register */

	u8  res3[48];

	u32 tmr_fiper1;   /* Timer fixed period interval */

	u32 tmr_fiper2;   /* Timer fixed period interval */

	u32 tmr_fiper3;   /* Timer fixed period interval */

	u8  res4[20];

	u32 tmr_etts1_h;  /* Timestamp of general purpose external trigger */

	u32 tmr_etts1_l;  /* Timestamp of general purpose external trigger */

	u32 tmr_etts2_h;  /* Timestamp of general purpose external trigger */

	u32 tmr_etts2_l;  /* Timestamp of general purpose external trigger */

};



/* Bit definitions for the TMR_CTRL register */

#define ALM1P                 (1<<31) /* Alarm1 output polarity */

#define ALM2P                 (1<<30) /* Alarm2 output polarity */

#define FIPERST               (1<<28) /* FIPER start indication */

#define PP1L                  (1<<27) /* Fiper1 pulse loopback mode enabled. */

#define PP2L                  (1<<26) /* Fiper2 pulse loopback mode enabled. */

#define TCLK_PERIOD_SHIFT     (16) /* 1588 timer reference clock period. */

#define TCLK_PERIOD_MASK      (0x3ff)

#define RTPE                  (1<<15) /* Record Tx Timestamp to PAL Enable. */

#define FRD                   (1<<14) /* FIPER Realignment Disable */

#define ESFDP                 (1<<11) /* External Tx/Rx SFD Polarity. */

#define ESFDE                 (1<<10) /* External Tx/Rx SFD Enable. */

#define ETEP2                 (1<<9) /* External trigger 2 edge polarity */

#define ETEP1                 (1<<8) /* External trigger 1 edge polarity */

#define COPH                  (1<<7) /* Generated clock output phase. */

#define CIPH                  (1<<6) /* External oscillator input clock phase */

#define TMSR                  (1<<5) /* Timer soft reset. */

#define BYP                   (1<<3) /* Bypass drift compensated clock */

#define TE                    (1<<2) /* 1588 timer enable. */

#define CKSEL_SHIFT           (0)    /* 1588 Timer reference clock source */

#define CKSEL_MASK            (0x3)



/* Bit definitions for the TMR_TEVENT register */

#define ETS2                  (1<<25) /* External trigger 2 timestamp sampled */

#define ETS1                  (1<<24) /* External trigger 1 timestamp sampled */

#define ALM2                  (1<<17) /* Current time = alarm time register 2 */

#define ALM1                  (1<<16) /* Current time = alarm time register 1 */

#define PP1                   (1<<7)  /* periodic pulse generated on FIPER1 */

#define PP2                   (1<<6)  /* periodic pulse generated on FIPER2 */

#define PP3                   (1<<5)  /* periodic pulse generated on FIPER3 */



/* Bit definitions for the TMR_TEMASK register */

#define ETS2EN                (1<<25) /* External trigger 2 timestamp enable */

#define ETS1EN                (1<<24) /* External trigger 1 timestamp enable */

#define ALM2EN                (1<<17) /* Timer ALM2 event enable */

#define ALM1EN                (1<<16) /* Timer ALM1 event enable */

#define PP1EN                 (1<<7) /* Periodic pulse event 1 enable */

#define PP2EN                 (1<<6) /* Periodic pulse event 2 enable */



/* Bit definitions for the TMR_PEVENT register */

#define TXP2                  (1<<9) /* PTP transmitted timestamp im TXTS2 */

#define TXP1                  (1<<8) /* PTP transmitted timestamp in TXTS1 */

#define RXP                   (1<<0) /* PTP frame has been received */



/* Bit definitions for the TMR_PEMASK register */

#define TXP2EN                (1<<9) /* Transmit PTP packet event 2 enable */

#define TXP1EN                (1<<8) /* Transmit PTP packet event 1 enable */

#define RXPEN                 (1<<0) /* Receive PTP packet event enable */



/* Bit definitions for the TMR_STAT register */

#define STAT_VEC_SHIFT        (0) /* Timer general purpose status vector */

#define STAT_VEC_MASK         (0x3f)



/* Bit definitions for the TMR_PRSC register */

#define PRSC_OCK_SHIFT        (0) /* Output clock division/prescale factor. */

#define PRSC_OCK_MASK         (0xffff)





#define DRIVER		"ptp_qoriq"

#define DEFAULT_CKSEL	1

#define N_EXT_TS	2

#define REG_SIZE	sizeof(struct qoriq_ptp_registers)



struct qoriq_ptp {

	struct qoriq_ptp_registers __iomem *regs;

	spinlock_t lock; /* protects regs */

	struct ptp_clock *clock;

	struct ptp_clock_info caps;

	struct resource *rsrc;

	int irq;

	int phc_index;

	u64 alarm_interval; /* for periodic alarm */

	u64 alarm_value;

	u32 tclk_period;  /* nanoseconds */

	u32 tmr_prsc;

	u32 tmr_add;

	u32 cksel;

	u32 tmr_fiper1;

	u32 tmr_fiper2;

};



static inline u32 qoriq_read(unsigned __iomem *addr)

{

	u32 val;



	val = ioread32be(addr);

	return val;

}



static inline void qoriq_write(unsigned __iomem *addr, u32 val)

{

	iowrite32be(val, addr);

}



#endif