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Commit 6c16816b authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/44x: use patch_sites for TLB handlers patching 



Use patch sites and associated helpers to manage TLB handlers
patching instead of hardcoding.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent d16952a6

arch/powerpc/include/asm/nohash/32/mmu-44x.h

+3 −0
Original line number Diff line number Diff line
@@ -111,6 +111,9 @@ typedef struct { 
	unsigned long	vdso_base;

} mm_context_t;



/* patch sites */

extern s32 patch__tlb_44x_hwater_D, patch__tlb_44x_hwater_I;



#endif /* !__ASSEMBLY__ */



#ifndef CONFIG_PPC_EARLY_DEBUG_44x

arch/powerpc/kernel/head_44x.S

+5 −6
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ 
#include <asm/ptrace.h>

#include <asm/synch.h>

#include <asm/export.h>

#include <asm/code-patching-asm.h>

#include "head_booke.h"
@@ -382,10 +383,9 @@ interrupt_base: 
	/* Increment, rollover, and store TLB index */

	addi	r13,r13,1



	patch_site 0f, patch__tlb_44x_hwater_D

	/* Compare with watermark (instruction gets patched) */

	.globl tlb_44x_patch_hwater_D

tlb_44x_patch_hwater_D:

	cmpwi	0,r13,1			/* reserve entries */

0:	cmpwi	0,r13,1			/* reserve entries */

	ble	5f

	li	r13,0

5:
@@ -478,10 +478,9 @@ tlb_44x_patch_hwater_D: 
	/* Increment, rollover, and store TLB index */

	addi	r13,r13,1



	patch_site 0f, patch__tlb_44x_hwater_I

	/* Compare with watermark (instruction gets patched) */

	.globl tlb_44x_patch_hwater_I

tlb_44x_patch_hwater_I:

	cmpwi	0,r13,1			/* reserve entries */

0:	cmpwi	0,r13,1			/* reserve entries */

	ble	5f

	li	r13,0

5:

arch/powerpc/mm/44x_mmu.c

+3 −11
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
#include <asm/mmu.h>

#include <asm/page.h>

#include <asm/cacheflush.h>

#include <asm/code-patching.h>



#include "mmu_decl.h"
@@ -43,22 +44,13 @@ unsigned long tlb_47x_boltmap[1024/8]; 


static void ppc44x_update_tlb_hwater(void)

{

	extern unsigned int tlb_44x_patch_hwater_D[];

	extern unsigned int tlb_44x_patch_hwater_I[];



	/* The TLB miss handlers hard codes the watermark in a cmpli

	 * instruction to improve performances rather than loading it

	 * from the global variable. Thus, we patch the instructions

	 * in the 2 TLB miss handlers when updating the value

	 */

	tlb_44x_patch_hwater_D[0] = (tlb_44x_patch_hwater_D[0] & 0xffff0000) |

		tlb_44x_hwater;

	flush_icache_range((unsigned long)&tlb_44x_patch_hwater_D[0],

			   (unsigned long)&tlb_44x_patch_hwater_D[1]);

	tlb_44x_patch_hwater_I[0] = (tlb_44x_patch_hwater_I[0] & 0xffff0000) |

		tlb_44x_hwater;

	flush_icache_range((unsigned long)&tlb_44x_patch_hwater_I[0],

			   (unsigned long)&tlb_44x_patch_hwater_I[1]);

	modify_instruction_site(&patch__tlb_44x_hwater_D, 0xffff, tlb_44x_hwater);

	modify_instruction_site(&patch__tlb_44x_hwater_I, 0xffff, tlb_44x_hwater);

}



/*