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Commit 6c00cac1 authored by Joseph Lo's avatar Joseph Lo Committed by Thierry Reding
Browse files

arm64: tegra: Add L2 cache topology to Tegra210 



Add L2 cache and make it the next level of cache for each of the CPUs.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 3056c1ca

arch/arm64/boot/dts/nvidia/tegra210.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -1372,6 +1372,7 @@ 
			clock-names = "cpu_g", "pll_x", "pll_p", "dfll";

			clock-latency = <300000>;

			cpu-idle-states = <&CPU_SLEEP>;

			next-level-cache = <&L2>;

		};



		cpu@1 {
@@ -1379,6 +1380,7 @@ 
			compatible = "arm,cortex-a57";

			reg = <1>;

			cpu-idle-states = <&CPU_SLEEP>;

			next-level-cache = <&L2>;

		};



		cpu@2 {
@@ -1386,6 +1388,7 @@ 
			compatible = "arm,cortex-a57";

			reg = <2>;

			cpu-idle-states = <&CPU_SLEEP>;

			next-level-cache = <&L2>;

		};



		cpu@3 {
@@ -1393,6 +1396,7 @@ 
			compatible = "arm,cortex-a57";

			reg = <3>;

			cpu-idle-states = <&CPU_SLEEP>;

			next-level-cache = <&L2>;

		};



		idle-states {
@@ -1409,6 +1413,10 @@ 
				status = "disabled";

			};

		};



		L2: l2-cache {

			compatible = "cache";

		};

	};



	timer {