Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6baefa1a authored by Alexei Starovoitov's avatar Alexei Starovoitov
Browse files

Merge branch 'support-alu32_arsh' 



Jiong Wang says:

====================
BPF_ALU | BPF_ARSH | BPF_* were rejected by commit: 7891a87e
("bpf: arsh is not supported in 32 bit alu thus reject it"). As explained
in the commit message, this is due to there is no complete support for them
on interpreter and various JIT compilation back-ends.

This patch set is a follow-up which completes the missing bits. This also
pave the way for running bpf program compiled with ALU32 instruction
enabled by specifing -mattr=+alu32 to LLVM for which case there is likely
to have more BPF_ALU | BPF_ARSH insns that will trigger the rejection code.

test_verifier.c is updated accordingly.

I have tested this patch set on x86-64 and NFP, I need help of review and
test on the arch changes (mips/ppc/s390).

Note, there might be merge confict on mips change which is better to be
applied on top of:

  commit: 20b880a05f06 ("mips: bpf: fix encoding bug for mm_srlv32_op"),

which is on mips-fixes branch at the moment.

Thanks.

v1->v2:
 - Fix ppc implementation bug. Should zero high bits explicitly.
====================

Signed-off-by: default avatarAlexei Starovoitov <ast@kernel.org>
parents 17f6c83f c099f3f4

arch/mips/include/asm/uasm.h

+1 −0
Original line number Diff line number Diff line
@@ -157,6 +157,7 @@ Ip_u2u1s3(_slti); 
Ip_u2u1s3(_sltiu);

Ip_u3u1u2(_sltu);

Ip_u2u1u3(_sra);

Ip_u3u2u1(_srav);

Ip_u2u1u3(_srl);

Ip_u3u2u1(_srlv);

Ip_u3u1u2(_subu);

arch/mips/include/uapi/asm/inst.h

+1 −0
Original line number Diff line number Diff line
@@ -371,6 +371,7 @@ enum mm_32a_minor_op { 
	mm_srl32_op = 0x040,

	mm_srlv32_op = 0x050,

	mm_sra_op = 0x080,

	mm_srav_op = 0x090,

	mm_rotr_op = 0x0c0,

	mm_lwxs_op = 0x118,

	mm_addu32_op = 0x150,

arch/mips/mm/uasm-micromips.c

+1 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ static const struct insn insn_table_MM[insn_invalid] = { 
	[insn_sltiu]	= {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},

	[insn_sltu]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD},

	[insn_sra]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD},

	[insn_srav]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_srav_op), RT | RS | RD},

	[insn_srl]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD},

	[insn_srlv]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD},

	[insn_rotr]	= {M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD},

arch/mips/mm/uasm-mips.c

+1 −0
Original line number Diff line number Diff line
@@ -171,6 +171,7 @@ static const struct insn insn_table[insn_invalid] = { 
	[insn_sltiu]	= {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

	[insn_sltu]	= {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD},

	[insn_sra]	= {M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE},

	[insn_srav]	= {M(spec_op, 0, 0, 0, 0, srav_op), RS | RT | RD},

	[insn_srl]	= {M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE},

	[insn_srlv]	= {M(spec_op, 0, 0, 0, 0, srlv_op),  RS | RT | RD},

	[insn_subu]	= {M(spec_op, 0, 0, 0, 0, subu_op),	RS | RT | RD},

arch/mips/mm/uasm.c

+5 −4
Original line number Diff line number Diff line
@@ -61,10 +61,10 @@ enum opcode { 
	insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_nor,

	insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb,

	insn_sc, insn_scd, insn_sd, insn_sh, insn_sll, insn_sllv,

	insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srl,

	insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp,

	insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor,

	insn_xori, insn_yield,

	insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srav,

	insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,

	insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh,

	insn_xor, insn_xori, insn_yield,

	insn_invalid /* insn_invalid must be last */

};
@@ -353,6 +353,7 @@ I_u2u1s3(_slti) 
I_u2u1s3(_sltiu)

I_u3u1u2(_sltu)

I_u2u1u3(_sra)

I_u3u2u1(_srav)

I_u2u1u3(_srl)

I_u3u2u1(_srlv)

I_u2u1u3(_rotr)