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Commit 6ba3f37f authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'samsung-soc-4.20-2' of... 

Merge tag 'samsung-soc-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/soc

Samsung mach/soc changes for v4.20, second round

1. Disable SAMSUNG_PM_CHECK Kconfig feature incompatible with Exynos.

* tag 'samsung-soc-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux

:
  ARM: samsung: Limit SAMSUNG_PM_CHECK config option to non-Exynos platforms
  ARM: s3c24xx: Restore proper usage of pr_info/pr_cont
  ARM: s3c24xx: Correct SD card write protect detection on Mini2440
  ARM: s3c24xx: Consistently use tab for indenting member assignments
  ARM: s3c24xx: formatting cleanup in mach-mini2440.c
  ARM: s3c24xx: Remove empty gta02_pmu children probe
  ARM: exynos: Fix imprecise abort during Exynos5422 suspend to RAM
  ARM: exynos: Store Exynos5420 register state in one variable

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 5220a73a 6862fdf2

Documentation/arm/Samsung/Bootloader-interface.txt

+1 −0
Original line number Original line Diff line number Diff line
@@ -26,6 +26,7 @@ Offset Value Purpose 
0x20          0xfcba0d10 (Magic cookie)                    AFTR

0x20          0xfcba0d10 (Magic cookie)                    AFTR

0x24          exynos_cpu_resume_ns                         AFTR

0x24          exynos_cpu_resume_ns                         AFTR

0x28 + 4*cpu  0x8 (Magic cookie, Exynos3250)               AFTR

0x28 + 4*cpu  0x8 (Magic cookie, Exynos3250)               AFTR

0x28          0x0 or last value during resume (Exynos542x) System suspend









2. Secure mode

2. Secure mode

arch/arm/mach-exynos/common.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -110,6 +110,7 @@ void exynos_firmware_init(void); 
#define EXYNOS_SLEEP_MAGIC	0x00000bad

#define EXYNOS_SLEEP_MAGIC	0x00000bad

#define EXYNOS_AFTR_MAGIC	0xfcba0d10

#define EXYNOS_AFTR_MAGIC	0xfcba0d10





bool __init exynos_secure_firmware_available(void);

void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);

void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);

void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);

void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);

arch/arm/mach-exynos/firmware.c

+11 −3
Original line number Original line Diff line number Diff line
@@ -185,7 +185,7 @@ static void exynos_l2_configure(const struct l2x0_regs *regs) 
	exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);

	exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);

}

}





void __init exynos_firmware_init(void)

bool __init exynos_secure_firmware_available(void)

{

{

	struct device_node *nd;

	struct device_node *nd;

	const __be32 *addr;

	const __be32 *addr;
@@ -193,14 +193,22 @@ void __init exynos_firmware_init(void) 
	nd = of_find_compatible_node(NULL, NULL,

	nd = of_find_compatible_node(NULL, NULL,

					"samsung,secure-firmware");

					"samsung,secure-firmware");

	if (!nd)

	if (!nd)

		return;

		return false;





	addr = of_get_address(nd, 0, NULL, NULL);

	addr = of_get_address(nd, 0, NULL, NULL);

	if (!addr) {

	if (!addr) {

		pr_err("%s: No address specified.\n", __func__);

		pr_err("%s: No address specified.\n", __func__);

		return;

		return false;

	}



	return true;

}

}





void __init exynos_firmware_init(void)

{

	if (!exynos_secure_firmware_available())

		return;



	pr_info("Running under secure firmware.\n");

	pr_info("Running under secure firmware.\n");





	register_firmware_ops(&exynos_firmware_ops);

	register_firmware_ops(&exynos_firmware_ops);

arch/arm/mach-exynos/suspend.c

+24 −10
Original line number Original line Diff line number Diff line
@@ -59,10 +59,15 @@ struct exynos_pm_data { 
	int (*cpu_suspend)(unsigned long);

	int (*cpu_suspend)(unsigned long);

};

};





static const struct exynos_pm_data *pm_data __ro_after_init;

/* Used only on Exynos542x/5800 */

struct exynos_pm_state {

	int cpu_state;

	unsigned int pmu_spare3;

	void __iomem *sysram_base;

};





static int exynos5420_cpu_state;

static const struct exynos_pm_data *pm_data __ro_after_init;

static unsigned int exynos_pmu_spare3;

static struct exynos_pm_state pm_state;





/*

/*

 * GIC wake-up support

 * GIC wake-up support
@@ -257,7 +262,7 @@ static int exynos5420_cpu_suspend(unsigned long arg) 
	unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);

	unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);

	unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);

	unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);





	writel_relaxed(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);

	writel_relaxed(0x0, pm_state.sysram_base + EXYNOS5420_CPU_STATE);





	if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {

	if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {

		mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);

		mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
@@ -321,7 +326,7 @@ static void exynos5420_pm_prepare(void) 
	/* Set wake-up mask registers */

	/* Set wake-up mask registers */

	exynos_pm_set_wakeup_mask();

	exynos_pm_set_wakeup_mask();





	exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);

	pm_state.pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);

	/*

	/*

	 * The cpu state needs to be saved and restored so that the

	 * The cpu state needs to be saved and restored so that the

	 * secondary CPUs will enter low power start. Though the U-Boot

	 * secondary CPUs will enter low power start. Though the U-Boot
@@ -329,7 +334,7 @@ static void exynos5420_pm_prepare(void) 
	 * needs to restore it back in case, the primary cpu fails to

	 * needs to restore it back in case, the primary cpu fails to

	 * suspend for any reason.

	 * suspend for any reason.

	 */

	 */

	exynos5420_cpu_state = readl_relaxed(sysram_base_addr +

	pm_state.cpu_state = readl_relaxed(pm_state.sysram_base +

					   EXYNOS5420_CPU_STATE);

					   EXYNOS5420_CPU_STATE);





	exynos_pm_enter_sleep_mode();

	exynos_pm_enter_sleep_mode();
@@ -448,8 +453,8 @@ static void exynos5420_pm_resume(void) 
		       EXYNOS5_ARM_CORE0_SYS_PWR_REG);

		       EXYNOS5_ARM_CORE0_SYS_PWR_REG);





	/* Restore the sysram cpu state register */

	/* Restore the sysram cpu state register */

	writel_relaxed(exynos5420_cpu_state,

	writel_relaxed(pm_state.cpu_state,

		       sysram_base_addr + EXYNOS5420_CPU_STATE);

		       pm_state.sysram_base + EXYNOS5420_CPU_STATE);





	pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,

	pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,

			S5P_CENTRAL_SEQ_OPTION);

			S5P_CENTRAL_SEQ_OPTION);
@@ -457,7 +462,7 @@ static void exynos5420_pm_resume(void) 
	if (exynos_pm_central_resume())

	if (exynos_pm_central_resume())

		goto early_wakeup;

		goto early_wakeup;





	pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);

	pmu_raw_writel(pm_state.pmu_spare3, S5P_PMU_SPARE3);





early_wakeup:

early_wakeup:
@@ -654,4 +659,13 @@ void __init exynos_pm_init(void) 




	register_syscore_ops(&exynos_pm_syscore_ops);

	register_syscore_ops(&exynos_pm_syscore_ops);

	suspend_set_ops(&exynos_suspend_ops);

	suspend_set_ops(&exynos_suspend_ops);



	/*

	 * Applicable as of now only to Exynos542x. If booted under secure

	 * firmware, the non-secure region of sysram should be used.

	 */

	if (exynos_secure_firmware_available())

		pm_state.sysram_base = sysram_ns_base_addr;

	else

		pm_state.sysram_base = sysram_base_addr;

}
 
}

arch/arm/mach-s3c24xx/mach-gta02.c

+0 −42
Original line number Original line Diff line number Diff line
@@ -219,17 +219,6 @@ static void gta02_udc_vbus_draw(unsigned int ma) 
#define gta02_udc_vbus_draw		NULL

#define gta02_udc_vbus_draw		NULL

#endif

#endif





/*

 * This is called when pc50633 is probed, unfortunately quite late in the

 * day since it is an I2C bus device. Here we can belatedly define some

 * platform devices with the advantage that we can mark the pcf50633 as the

 * parent. This makes them get suspended and resumed with their parent

 * the pcf50633 still around.

 */



static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf);





static char *gta02_batteries[] = {

static char *gta02_batteries[] = {

	"battery",

	"battery",

};

};
@@ -355,7 +344,6 @@ static struct pcf50633_platform_data gta02_pcf_pdata = { 
		},

		},





	},

	},

	.probe_done = gta02_pmu_attach_child_devices,

	.mbc_event_callback = gta02_pmu_event_callback,

	.mbc_event_callback = gta02_pmu_event_callback,

};

};
@@ -512,36 +500,6 @@ static struct platform_device *gta02_devices[] __initdata = { 
	&s3c_device_ts,

	&s3c_device_ts,

};

};





/* These guys DO need to be children of PMU. */



static struct platform_device *gta02_devices_pmu_children[] = {

};





/*

 * This is called when pc50633 is probed, quite late in the day since it is an

 * I2C bus device.  Here we can define platform devices with the advantage that

 * we can mark the pcf50633 as the parent.  This makes them get suspended and

 * resumed with their parent the pcf50633 still around.  All devices whose

 * operation depends on something from pcf50633 must have this relationship

 * made explicit like this, or suspend and resume will become an unreliable

 * hellworld.

 */



static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf)

{

	int n;



	/* Grab a copy of the now probed PMU pointer. */

	gta02_pcf = pcf;



	for (n = 0; n < ARRAY_SIZE(gta02_devices_pmu_children); n++)

		gta02_devices_pmu_children[n]->dev.parent = pcf->dev;



	platform_add_devices(gta02_devices_pmu_children,

			     ARRAY_SIZE(gta02_devices_pmu_children));

}



static void gta02_poweroff(void)

static void gta02_poweroff(void)

{

{

	pcf50633_reg_set_bit_mask(gta02_pcf, PCF50633_REG_OOCSHDWN, 1, 1);

	pcf50633_reg_set_bit_mask(gta02_pcf, PCF50633_REG_OOCSHDWN, 1, 1);