Loading qcom/lahaina-usb.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -12,6 +12,7 @@ ranges; dma-ranges; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>, <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, Loading Loading @@ -55,6 +56,7 @@ ranges; dma-ranges; USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>; clocks = <&clock_gcc GCC_USB30_SEC_MASTER_CLK>, <&clock_gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, Loading Loading
qcom/lahaina-usb.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -12,6 +12,7 @@ ranges; dma-ranges; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>, <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, Loading Loading @@ -55,6 +56,7 @@ ranges; dma-ranges; USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>; clocks = <&clock_gcc GCC_USB30_SEC_MASTER_CLK>, <&clock_gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, Loading