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Commit 6ae8ec27 authored by Rafał Miłecki's avatar Rafał Miłecki Committed by John W. Linville
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ssb: fix init regression of hostmode PCI core 



Our workarounds seem to be clientmode PCI specific. Using SPROM
workaround on SoC resulted in Oops:

Data bus error, epc == 8017ed58, ra == 80225838
 Oops[#1]:
 Cpu 0
 $ 0   : 00000000 10008000 b8000000 00000001
 $ 4   : 80293b5c 00000caa ffffffff 00000000
 $ 8   : 0000000a 00000003 00000001 696d6d20
 $12   : ffffffff 00000000 00000000 ffffffff
 $16   : 802d0140 b8004800 802c0000 00000000
 $20   : 00000000 802c0000 00000000 802d04d4
 $24   : 00000018 80151a00
 $28   : 81816000 81817df8 8029bda0 80225838
 Hi    : 00000000
 Lo    : 00000000
 epc   : 8017ed58 ssb_ssb_read16+0x48/0x60
   Not tainted
 ra    : 80225838 ssb_pcicore_init+0x54/0x3b4

Reported-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: default avatarRafał Miłecki <zajec5@gmail.com>
Tested-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 35cbcbc6

drivers/ssb/driver_pcicore.c

+9 −9
Original line number Original line Diff line number Diff line
@@ -516,8 +516,17 @@ static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc) 




static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)

static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)

{

{

	ssb_pcicore_fix_sprom_core_index(pc);



	/* Disable PCI interrupts. */

	/* Disable PCI interrupts. */

	ssb_write32(pc->dev, SSB_INTVEC, 0);

	ssb_write32(pc->dev, SSB_INTVEC, 0);



	/* Additional PCIe always once-executed workarounds */

	if (pc->dev->id.coreid == SSB_DEV_PCIE) {

		ssb_pcicore_serdes_workaround(pc);

		/* TODO: ASPM */

		/* TODO: Clock Request Update */

	}

}

}





void ssb_pcicore_init(struct ssb_pcicore *pc)

void ssb_pcicore_init(struct ssb_pcicore *pc)
@@ -529,8 +538,6 @@ void ssb_pcicore_init(struct ssb_pcicore *pc) 
	if (!ssb_device_is_enabled(dev))

	if (!ssb_device_is_enabled(dev))

		ssb_device_enable(dev, 0);

		ssb_device_enable(dev, 0);





	ssb_pcicore_fix_sprom_core_index(pc);



#ifdef CONFIG_SSB_PCICORE_HOSTMODE

#ifdef CONFIG_SSB_PCICORE_HOSTMODE

	pc->hostmode = pcicore_is_in_hostmode(pc);

	pc->hostmode = pcicore_is_in_hostmode(pc);

	if (pc->hostmode)

	if (pc->hostmode)
@@ -538,13 +545,6 @@ void ssb_pcicore_init(struct ssb_pcicore *pc) 
#endif /* CONFIG_SSB_PCICORE_HOSTMODE */

#endif /* CONFIG_SSB_PCICORE_HOSTMODE */

	if (!pc->hostmode)

	if (!pc->hostmode)

		ssb_pcicore_init_clientmode(pc);

		ssb_pcicore_init_clientmode(pc);



	/* Additional PCIe always once-executed workarounds */

	if (dev->id.coreid == SSB_DEV_PCIE) {

		ssb_pcicore_serdes_workaround(pc);

		/* TODO: ASPM */

		/* TODO: Clock Request Update */

	}

}

}





static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)

static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)