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Commit 6acbb2de authored by Venkata Prahlad Valluru's avatar Venkata Prahlad Valluru Committed by Gerrit - the friendly Code Review server
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disp: msm: typecast variables as long long for 64 bit operations 



Define 64 bit variables as unsigned long long to ensure
8 bytes in 32 bit builds.

Change-Id: I723ae0c4ba6a0de07c92d14eeef95bde095c8e3d
Signed-off-by: default avatarVenkata Prahlad Valluru <vvalluru@codeaurora.org>
parent 6eab4345

msm/dsi/dsi_pll_5nm.c

+7 −7
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.

 */



#define pr_fmt(fmt)	"%s: " fmt, __func__
@@ -565,11 +565,11 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_5nm *pll, 
	switch (rsc->pll_revision) {

	case DSI_PLL_5NM:

	default:

		if (pll_freq <= 1000000000)

		if (pll_freq <= 1000000000ULL)

			regs->pll_clock_inverters = 0xA0;

		else if (pll_freq <= 2500000000)

		else if (pll_freq <= 2500000000ULL)

			regs->pll_clock_inverters = 0x20;

		else if (pll_freq <= 3500000000)

		else if (pll_freq <= 3500000000ULL)

			regs->pll_clock_inverters = 0x00;

		else

			regs->pll_clock_inverters = 0x40;
@@ -664,16 +664,16 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_5nm *pll, 
	switch (rsc->pll_revision) {

	case DSI_PLL_5NM:

	default:

		if (vco_rate < 3100000000)

		if (vco_rate < 3100000000ULL)

			DSI_PLL_REG_W(pll_base,

					PLL_ANALOG_CONTROLS_FIVE_1, 0x01);

		else

			DSI_PLL_REG_W(pll_base,

					PLL_ANALOG_CONTROLS_FIVE_1, 0x03);



		if (vco_rate < 1520000000)

		if (vco_rate < 1520000000ULL)

			DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x08);

		else if (vco_rate < 2990000000)

		else if (vco_rate < 2990000000ULL)

			DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00);

		else

			DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x01);

msm/sde/sde_hw_color_proc_v4.c

+2 −2
Original line number Diff line number Diff line
@@ -423,8 +423,8 @@ void sde_demura_backlight_cfg(struct sde_hw_dspp *dspp, u64 val) 
		return;

	}

	demura_base = dspp->cap->sblk->demura.base;

	backlight = (val & REG_MASK(11));

	backlight |= ((val & REG_MASK_SHIFT(11, 32)) >> 16);

	backlight = (val & REG_MASK_ULL(11));

	backlight |= ((val & REG_MASK_SHIFT_ULL(11, 32)) >> 16);

	SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->demura.base + 0x8,

			backlight);

}

msm/sde/sde_hw_reg_dma_v1.c

+2 −1
Original line number Diff line number Diff line
@@ -880,7 +880,8 @@ static int check_support_v1(enum sde_reg_dma_features feature, 
	if (!is_supported)

		return -EINVAL;



	if (feature >= REG_DMA_FEATURES_MAX || blk >= BIT(REG_DMA_BLK_MAX)) {

	if (feature >= REG_DMA_FEATURES_MAX

		|| blk >= BIT_ULL(REG_DMA_BLK_MAX)) {

		*is_supported = false;

		return ret;

	}

msm/sde/sde_hw_reg_dma_v1_color_proc.c

+3 −4
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include "sde_hwio.h"

#include "sde_hw_lm.h"

#include "sde_dbg.h"

#include "sde_hw_util.h"



/* Reserve space of 128 words for LUT dma payload set-up */

#define REG_DMA_HEADERS_BUFFER_SZ (sizeof(u32) * 128)
@@ -84,8 +85,6 @@ 
#define DEMURA_MEM_SIZE ((sizeof(struct drm_msm_dem_cfg)) + \

		REG_DMA_HEADERS_BUFFER_SZ)



#define REG_MASK(n) ((BIT(n)) - 1)

#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))

#define APPLY_MASK_AND_SHIFT(x, n, shift) ((x & (REG_MASK(n))) << (shift))

#define REG_DMA_VIG_GAMUT_OP_MASK 0x300

#define REG_DMA_VIG_IGC_OP_MASK 0x1001F
@@ -4926,8 +4925,8 @@ static int __reg_dmav1_setup_demurav1_cfg0_c_params( 
	}



	for (i = 0; i < len; i++) {

		temp[i * 2] = p[i] & REG_MASK(32);

		temp[i * 2 + 1] = (p[i] & REG_MASK_SHIFT(10, 32)) >> 32;

		temp[i * 2] = p[i] & REG_MASK_ULL(32);

		temp[i * 2 + 1] = (p[i] & REG_MASK_SHIFT_ULL(10, 32)) >> 32;

		DRM_DEBUG_DRIVER("0x6c: index %d value %x\n",

				i * 2, temp[i * 2]);

		DRM_DEBUG_DRIVER("0x6c: index %d value %x\n",

msm/sde/sde_hw_util.h

+4 −2
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.

 */



#ifndef _SDE_HW_UTIL_H
@@ -13,6 +13,8 @@ 


#define REG_MASK(n)                     ((BIT(n)) - 1)

#define REG_MASK_SHIFT(n, shift)        ((REG_MASK(n)) << (shift))

#define REG_MASK_ULL(n)                 ((BIT_ULL(n)) - 1)

#define REG_MASK_SHIFT_ULL(n, shift)    ((REG_MASK_ULL(n)) << (shift))

#define LP_DDR4_TYPE			0x7



struct sde_format_extended;