Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Unverified Commit 6a1cc218 authored by Paul Burton's avatar Paul Burton
Browse files

MIPS: branch: Remove FP branch handling when CONFIG_MIPS_FP_SUPPORT=n 



When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so remove
the floating point branch support from __compute_return_epc_for_insn() &
__mm_isBranchInstr(). This code should never be needed & more
importantly relies upon FPU state in struct task_struct which will later
be removed.

Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/21017/
Cc: linux-mips@linux-mips.org
parent 5328f742

arch/mips/kernel/branch.c

+16 −6
Original line number Diff line number Diff line
@@ -58,9 +58,6 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 
		       unsigned long *contpc)

{

	union mips_instruction insn = (union mips_instruction)dec_insn.insn;

	int bc_false = 0;

	unsigned int fcr31;

	unsigned int bit;



	if (!cpu_has_mmips)

		return 0;
@@ -139,8 +136,13 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 
					dec_insn.pc_inc +

					dec_insn.next_pc_inc;

			return 1;

#ifdef CONFIG_MIPS_FP_SUPPORT

		case mm_bc2f_op:

		case mm_bc1f_op:

		case mm_bc1f_op: {

			int bc_false = 0;

			unsigned int fcr31;

			unsigned int bit;



			bc_false = 1;

			/* Fall through */

		case mm_bc2t_op:
@@ -167,6 +169,8 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 
					dec_insn.pc_inc + dec_insn.next_pc_inc;

			return 1;

		}

#endif /* CONFIG_MIPS_FP_SUPPORT */

		}

		break;

	case mm_pool16c_op:

		switch (insn.mm_i_format.rt) {
@@ -416,8 +420,8 @@ int __MIPS16e_compute_return_epc(struct pt_regs *regs) 
int __compute_return_epc_for_insn(struct pt_regs *regs,

				   union mips_instruction insn)

{

	unsigned int bit, fcr31, dspcontrol, reg;

	long epc = regs->cp0_epc;

	unsigned int dspcontrol;

	int ret = 0;



	switch (insn.i_format.opcode) {
@@ -667,10 +671,13 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, 
		regs->cp0_epc = epc;

		break;



#ifdef CONFIG_MIPS_FP_SUPPORT

	/*

	 * And now the FPA/cp1 branch instructions.

	 */

	case cop1_op:

	case cop1_op: {

		unsigned int bit, fcr31, reg;



		if (cpu_has_mips_r6 &&

		    ((insn.i_format.rs == bc1eqz_op) ||

		     (insn.i_format.rs == bc1nez_op))) {
@@ -728,6 +735,9 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, 
			}

			break;

		}

	}

#endif /* CONFIG_MIPS_FP_SUPPORT */



#ifdef CONFIG_CPU_CAVIUM_OCTEON

	case lwc2_op: /* This is bbit0 on Octeon */

		if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))