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Commit 6a157f7d authored by Yangyang Li's avatar Yangyang Li Committed by Jason Gunthorpe
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RDMA/hns: Add SCC context allocation support for hip08 



This patch adds SCC context allocation and initialization support for
DCQCN in kernel space driver.

Signed-off-by: default avatarYangyang Li <liyangyang20@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
parent 61b2fe3c

drivers/infiniband/hw/hns/hns_roce_cmd.h

+4 −0
Original line number Diff line number Diff line
@@ -98,6 +98,10 @@ enum { 
	HNS_ROCE_CMD_MODIFY_CEQC	= 0x91,

	HNS_ROCE_CMD_QUERY_CEQC		= 0x92,

	HNS_ROCE_CMD_DESTROY_CEQC	= 0x93,



	/* SCC CTX BT commands */

	HNS_ROCE_CMD_READ_SCCC_BT0	= 0xa4,

	HNS_ROCE_CMD_WRITE_SCCC_BT0	= 0xa5,

};



enum {

drivers/infiniband/hw/hns/hns_roce_device.h

+6 −0
Original line number Diff line number Diff line
@@ -482,6 +482,7 @@ struct hns_roce_qp_table { 
	struct hns_roce_hem_table	qp_table;

	struct hns_roce_hem_table	irrl_table;

	struct hns_roce_hem_table	trrl_table;

	struct hns_roce_hem_table	sccc_table;

};



struct hns_roce_cq_table {
@@ -768,6 +769,7 @@ struct hns_roce_caps { 
	int		irrl_entry_sz;

	int		trrl_entry_sz;

	int		cqc_entry_sz;

	int		sccc_entry_sz;

	int		srqc_entry_sz;

	int		idx_entry_sz;

	u32		pbl_ba_pg_sz;
@@ -780,6 +782,7 @@ struct hns_roce_caps { 
	u32		srqc_bt_num;

	u32		cqc_bt_num;

	u32		mpt_bt_num;

	u32		sccc_bt_num;

	u32		qpc_ba_pg_sz;

	u32		qpc_buf_pg_sz;

	u32		qpc_hop_num;
@@ -795,6 +798,9 @@ struct hns_roce_caps { 
	u32		mtt_ba_pg_sz;

	u32		mtt_buf_pg_sz;

	u32		mtt_hop_num;

	u32		sccc_ba_pg_sz;

	u32		sccc_buf_pg_sz;

	u32		sccc_hop_num;

	u32		cqe_ba_pg_sz;

	u32		cqe_buf_pg_sz;

	u32		cqe_hop_num;

drivers/infiniband/hw/hns/hns_roce_hem.c

+23 −3
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ bool hns_roce_check_whether_mhop(struct hns_roce_dev *hr_dev, u32 type) 
	    (hr_dev->caps.mpt_hop_num && type == HEM_TYPE_MTPT) ||

	    (hr_dev->caps.cqc_hop_num && type == HEM_TYPE_CQC) ||

	    (hr_dev->caps.srqc_hop_num && type == HEM_TYPE_SRQC) ||

	    (hr_dev->caps.sccc_hop_num && type == HEM_TYPE_SCCC) ||

	    (hr_dev->caps.cqe_hop_num && type == HEM_TYPE_CQE) ||

	    (hr_dev->caps.mtt_hop_num && type == HEM_TYPE_MTT) ||

	    (hr_dev->caps.srqwqe_hop_num && type == HEM_TYPE_SRQWQE) ||
@@ -125,6 +126,14 @@ int hns_roce_calc_hem_mhop(struct hns_roce_dev *hr_dev, 
		mhop->ba_l0_num = hr_dev->caps.cqc_bt_num;

		mhop->hop_num = hr_dev->caps.cqc_hop_num;

		break;

	case HEM_TYPE_SCCC:

		mhop->buf_chunk_size = 1 << (hr_dev->caps.sccc_buf_pg_sz

					     + PAGE_SHIFT);

		mhop->bt_chunk_size = 1 << (hr_dev->caps.sccc_ba_pg_sz

					    + PAGE_SHIFT);

		mhop->ba_l0_num = hr_dev->caps.sccc_bt_num;

		mhop->hop_num = hr_dev->caps.sccc_hop_num;

		break;

	case HEM_TYPE_SRQC:

		mhop->buf_chunk_size = 1 << (hr_dev->caps.srqc_buf_pg_sz

					     + PAGE_SHIFT);
@@ -175,7 +184,7 @@ int hns_roce_calc_hem_mhop(struct hns_roce_dev *hr_dev, 
		return 0;



	/*

	 * QPC/MTPT/CQC/SRQC alloc hem for buffer pages.

	 * QPC/MTPT/CQC/SRQC/SCCC alloc hem for buffer pages.

	 * MTT/CQE alloc hem for bt pages.

	 */

	bt_num = hns_roce_get_bt_num(table->type, mhop->hop_num);
@@ -486,7 +495,7 @@ static int hns_roce_table_mhop_get(struct hns_roce_dev *hr_dev, 
	}



	/*

	 * alloc buffer space chunk for QPC/MTPT/CQC/SRQC.

	 * alloc buffer space chunk for QPC/MTPT/CQC/SRQC/SCCC.

	 * alloc bt space chunk for MTT/CQE.

	 */

	size = table->type < HEM_TYPE_MTT ? buf_chunk_size : bt_chunk_size;
@@ -658,7 +667,7 @@ static void hns_roce_table_mhop_put(struct hns_roce_dev *hr_dev, 
	}



	/*

	 * free buffer space chunk for QPC/MTPT/CQC/SRQC.

	 * free buffer space chunk for QPC/MTPT/CQC/SRQC/SCCC.

	 * free bt space chunk for MTT/CQE.

	 */

	hns_roce_free_hem(hr_dev, table->hem[hem_idx]);
@@ -904,6 +913,14 @@ int hns_roce_init_hem_table(struct hns_roce_dev *hr_dev, 
			num_bt_l0 = hr_dev->caps.cqc_bt_num;

			hop_num = hr_dev->caps.cqc_hop_num;

			break;

		case HEM_TYPE_SCCC:

			buf_chunk_size = 1 << (hr_dev->caps.sccc_buf_pg_sz

					+ PAGE_SHIFT);

			bt_chunk_size = 1 << (hr_dev->caps.sccc_ba_pg_sz

					+ PAGE_SHIFT);

			num_bt_l0 = hr_dev->caps.sccc_bt_num;

			hop_num = hr_dev->caps.sccc_hop_num;

			break;

		case HEM_TYPE_SRQC:

			buf_chunk_size = 1 << (hr_dev->caps.srqc_buf_pg_sz

					+ PAGE_SHIFT);
@@ -1081,6 +1098,9 @@ void hns_roce_cleanup_hem(struct hns_roce_dev *hr_dev) 
		hns_roce_cleanup_hem_table(hr_dev,

					   &hr_dev->srq_table.table);

	hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);

	if (hr_dev->caps.sccc_entry_sz)

		hns_roce_cleanup_hem_table(hr_dev,

					   &hr_dev->qp_table.sccc_table);

	if (hr_dev->caps.trrl_entry_sz)

		hns_roce_cleanup_hem_table(hr_dev,

					   &hr_dev->qp_table.trrl_table);

drivers/infiniband/hw/hns/hns_roce_hem.h

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ enum { 
	HEM_TYPE_MTPT,

	HEM_TYPE_CQC,

	HEM_TYPE_SRQC,

	HEM_TYPE_SCCC,



	 /* UNMAP HEM */

	HEM_TYPE_MTT,

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+45 −1
Original line number Diff line number Diff line
@@ -1078,6 +1078,9 @@ static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 
	hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num,

					     PF_RES_DATA_3_PF_SL_NUM_M,

					     PF_RES_DATA_3_PF_SL_NUM_S);

	hr_dev->caps.sccc_bt_num = roce_get_field(req_b->sccc_bt_idx_num,

					     PF_RES_DATA_4_PF_SCCC_BT_NUM_M,

					     PF_RES_DATA_4_PF_SCCC_BT_NUM_S);



	return 0;

}
@@ -1193,6 +1196,14 @@ static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 
				       VF_RES_B_DATA_3_VF_SL_NUM_M,

				       VF_RES_B_DATA_3_VF_SL_NUM_S,

				       HNS_ROCE_VF_SL_NUM);



			roce_set_field(req_b->vf_sccc_idx_num,

				       VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M,

				       VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S, 0);

			roce_set_field(req_b->vf_sccc_idx_num,

				       VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M,

				       VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S,

				       HNS_ROCE_VF_SCCC_BT_NUM);

		}

	}
@@ -1205,6 +1216,7 @@ static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 
	u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;

	u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;

	u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;

	u8 sccc_hop_num = hr_dev->caps.sccc_hop_num;

	struct hns_roce_cfg_bt_attr *req;

	struct hns_roce_cmq_desc desc;
@@ -1252,6 +1264,20 @@ static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 
		       CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,

		       mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);



	roce_set_field(req->vf_sccc_cfg,

		       CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M,

		       CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S,

		       hr_dev->caps.sccc_ba_pg_sz + PG_SHIFT_OFFSET);

	roce_set_field(req->vf_sccc_cfg,

		       CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M,

		       CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S,

		       hr_dev->caps.sccc_buf_pg_sz + PG_SHIFT_OFFSET);

	roce_set_field(req->vf_sccc_cfg,

		       CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M,

		       CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S,

		       sccc_hop_num ==

			      HNS_ROCE_HOP_NUM_0 ? 0 : sccc_hop_num);



	return hns_roce_cmq_send(hr_dev, &desc, 1);

}
@@ -1408,9 +1434,14 @@ static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 
	caps->max_srq_wrs	= HNS_ROCE_V2_MAX_SRQ_WR;

	caps->max_srq_sges	= HNS_ROCE_V2_MAX_SRQ_SGE;



	if (hr_dev->pci_dev->revision == 0x21)

	if (hr_dev->pci_dev->revision == 0x21) {

		caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC |

			       HNS_ROCE_CAP_FLAG_SRQ;

		caps->sccc_entry_sz	= HNS_ROCE_V2_SCCC_ENTRY_SZ;

		caps->sccc_ba_pg_sz	= 0;

		caps->sccc_buf_pg_sz    = 0;

		caps->sccc_hop_num	= HNS_ROCE_SCCC_HOP_NUM;

	}



	ret = hns_roce_v2_set_bt(hr_dev);

	if (ret)
@@ -2663,11 +2694,18 @@ static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 
	case HEM_TYPE_SRQC:

		op = HNS_ROCE_CMD_WRITE_SRQC_BT0;

		break;

	case HEM_TYPE_SCCC:

		op = HNS_ROCE_CMD_WRITE_SCCC_BT0;

		break;

	default:

		dev_warn(dev, "Table %d not to be written by mailbox!\n",

			 table->type);

		return 0;

	}



	if (table->type == HEM_TYPE_SCCC && step_idx)

		return 0;



	op += step_idx;



	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
@@ -2722,6 +2760,8 @@ static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 
	case HEM_TYPE_CQC:

		op = HNS_ROCE_CMD_DESTROY_CQC_BT0;

		break;

	case HEM_TYPE_SCCC:

		break;

	case HEM_TYPE_SRQC:

		op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;

		break;
@@ -2730,6 +2770,10 @@ static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 
			 table->type);

		return 0;

	}



	if (table->type == HEM_TYPE_SCCC)

		return 0;



	op += step_idx;



	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);