Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Unverified Commit 69a07a41 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer Committed by Paul Burton
Browse files

MIPS: SGI-IP27: rework HUB interrupts



This commit rearranges the HUB interrupt code by using MIPS_IRQ_CPU
interrupt handling code and modern Linux IRQ framework features to get
rid of global arrays. It also adds support for irq affinity setting.

Signed-off-by: default avatarThomas Bogendoerfer <tbogendoerfer@suse.de>
Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
parent 2c865620
Loading
Loading
Loading
Loading
+1 −0
Original line number Diff line number Diff line
@@ -675,6 +675,7 @@ config SGI_IP27
	select DEFAULT_SGI_PARTITION
	select SYS_HAS_EARLY_PRINTK
	select HAVE_PCI
	select IRQ_MIPS_CPU
	select NR_CPUS_DEFAULT_64
	select SYS_HAS_CPU_R10000
	select SYS_SUPPORTS_64BIT_KERNEL
+7 −5
Original line number Diff line number Diff line
@@ -10,13 +10,15 @@
#ifndef __ASM_MACH_IP27_IRQ_H
#define __ASM_MACH_IP27_IRQ_H

/*
 * A hardwired interrupt number is completely stupid for this system - a
 * large configuration might have thousands if not tenthousands of
 * interrupts.
 */
#define NR_IRQS 256

#include_next <irq.h>

#define IP27_HUB_PEND0_IRQ	(MIPS_CPU_IRQ_BASE + 2)
#define IP27_HUB_PEND1_IRQ	(MIPS_CPU_IRQ_BASE + 3)
#define IP27_RT_TIMER_IRQ	(MIPS_CPU_IRQ_BASE + 4)

#define IP27_HUB_IRQ_BASE	(MIPS_CPU_IRQ_BASE + 8)
#define IP27_HUB_IRQ_COUNT	128

#endif /* __ASM_MACH_IP27_IRQ_H */
+0 −9
Original line number Diff line number Diff line
@@ -8,20 +8,11 @@

#define pa_to_nid(addr)		NASID_TO_COMPACT_NODEID(NASID_GET(addr))

#define LEVELS_PER_SLICE	128

struct slice_data {
	unsigned long irq_enable_mask[2];
	int level_to_irq[LEVELS_PER_SLICE];
};

struct hub_data {
	kern_vars_t	kern_vars;
	DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW);
	cpumask_t	h_cpus;
	unsigned long slice_map;
	unsigned long irq_alloc_mask[2];
	struct slice_data slice[2];
};

struct node_data {
+1 −3
Original line number Diff line number Diff line
@@ -808,7 +808,6 @@ struct bridge_controller {
	struct bridge_regs	*base;
	nasid_t			nasid;
	unsigned int		widget_id;
	unsigned int		irq_cpu;
	u64			baddr;
	unsigned int		pci_int[8];
};
@@ -823,8 +822,7 @@ struct bridge_controller {
#define bridge_clr(bc, reg, val)	\
	__raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)

extern void register_bridge_irq(unsigned int irq);
extern int request_bridge_irq(struct bridge_controller *bc);
extern int request_bridge_irq(struct bridge_controller *bc, int pin);

extern struct pci_ops bridge_pci_ops;

+1 −17
Original line number Diff line number Diff line
@@ -23,23 +23,12 @@
 */
#define MAX_PCI_BUSSES		40

/*
 * Max #PCI devices (like scsi controllers) we handle on a bus.
 */
#define MAX_DEVICES_PER_PCIBUS	8

/*
 * XXX: No kmalloc available when we do our crosstalk scan,
 *	we should try to move it later in the boot process.
 */
static struct bridge_controller bridges[MAX_PCI_BUSSES];

/*
 * Translate from irq to software PCI bus number and PCI slot.
 */
struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];

extern struct pci_ops bridge_pci_ops;

int bridge_probe(nasid_t nasid, int widget_id, int masterwid)
@@ -77,7 +66,6 @@ int bridge_probe(nasid_t nasid, int widget_id, int masterwid)
	bc->io.end		= ~0UL;
	bc->io.flags		= IORESOURCE_IO;

	bc->irq_cpu = smp_processor_id();
	bc->widget_id = widget_id;
	bc->nasid = nasid;

@@ -165,16 +153,12 @@ int pcibios_plat_dev_init(struct pci_dev *dev)

	irq = bc->pci_int[slot];
	if (irq == -1) {
		irq = request_bridge_irq(bc);
		irq = request_bridge_irq(bc, slot);
		if (irq < 0)
			return irq;

		bc->pci_int[slot] = irq;
	}

	irq_to_bridge[irq] = bc;
	irq_to_slot[irq] = slot;

	dev->irq = irq;

	return 0;
Loading