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Commit 6989303a authored by Marc Zyngier's avatar Marc Zyngier Committed by Will Deacon
Browse files

arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1 



Neoverse-N1 is also affected by ARM64_ERRATUM_1188873, so let's
add it to the list of affected CPUs.

Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
[will: Update silicon-errata.txt]
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 0cf57b86

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ stable kernels. 
| ARM            | Cortex-A76      | #1188873        | ARM64_ERRATUM_1188873       |

| ARM            | Cortex-A76      | #1165522        | ARM64_ERRATUM_1165522       |

| ARM            | Cortex-A76      | #1286807        | ARM64_ERRATUM_1286807       |

| ARM            | Neoverse-N1     | #1188873        | ARM64_ERRATUM_1188873       |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

arch/arm64/Kconfig

+6 −5
Original line number Diff line number Diff line
@@ -475,16 +475,17 @@ config ARM64_ERRATUM_1024718 
	  If unsure, say Y.



config ARM64_ERRATUM_1188873

	bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"

	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"

	default y

	depends on COMPAT

	select ARM_ARCH_TIMER_OOL_WORKAROUND

	help

	  This option adds work arounds for ARM Cortex-A76 erratum 1188873

	  This option adds work arounds for ARM Cortex-A76/Neoverse-N1

	  erratum 1188873



	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause

	  register corruption when accessing the timer registers from

	  AArch32 userspace.

	  Affected Cortex-A76/Neoverse-N1 cores (r0p0, r1p0, r2p0) could

	  cause register corruption when accessing the timer registers

	  from AArch32 userspace.



	  If unsure, say Y.

arch/arm64/kernel/cpu_errata.c

+11 −2
Original line number Diff line number Diff line
@@ -603,6 +603,16 @@ static const struct midr_range workaround_clean_cache[] = { 
};

#endif



#ifdef CONFIG_ARM64_ERRATUM_1188873

static const struct midr_range erratum_1188873_list[] = {

	/* Cortex-A76 r0p0 to r2p0 */

	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),

	/* Neoverse-N1 r0p0 to r2p0 */

	MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 2, 0),

	{},

};

#endif



const struct arm64_cpu_capabilities arm64_errata[] = {

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE

	{
@@ -725,10 +735,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
#endif

#ifdef CONFIG_ARM64_ERRATUM_1188873

	{

		/* Cortex-A76 r0p0 to r2p0 */

		.desc = "ARM erratum 1188873",

		.capability = ARM64_WORKAROUND_1188873,

		ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),

		ERRATA_MIDR_RANGE_LIST(erratum_1188873_list),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1165522