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Commit 68ff2ae5 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Check correct register for clamps on a660"

parents e25e97f3 98705af6

drivers/gpu/msm/a6xx_reg.h

+3 −1
Original line number Diff line number Diff line
@@ -1055,6 +1055,8 @@ 
/* GPUCC registers */

#define A6XX_GPU_CC_GX_GDSCR                   0x24403

#define A6XX_GPU_CC_GX_DOMAIN_MISC             0x24542

#define A6XX_GPU_CC_GX_DOMAIN_MISC3            0x24563





/* GPU RSC sequencer registers */

#define A6XX_GPU_RSCC_RSC_STATUS0_DRV0			0x00004

drivers/gpu/msm/adreno_a6xx_gmu.c

+7 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 */



/* soc/qcom/cmd-db.h needs types.h */
@@ -408,7 +408,12 @@ static int a6xx_rpmh_power_on_gpu(struct kgsl_device *device) 
	if (!test_bit(GMU_RSCC_SLEEP_SEQ_DONE, &device->gmu_core.flags))

		return 0;



	 /* A660 has a replacement register */

	if (adreno_is_a660(ADRENO_DEVICE(device)))

		gmu_core_regread(device, A6XX_GPU_CC_GX_DOMAIN_MISC3, &val);

	else

		gmu_core_regread(device, A6XX_GPU_CC_GX_DOMAIN_MISC, &val);



	if (!(val & 0x1))

		dev_err_ratelimited(&gmu->pdev->dev,

			"GMEM CLAMP IO not set while GFX rail off\n");