Merge "msm: kgsl: Print always on counters if fenced write timed out" (6874a5bd) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/gpu/msm/adreno.c

+6 −3

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved.
		* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
		*/
		#include <linux/component.h>
		#include <linux/delay.h>
		@@ -3131,12 +3132,14 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,
		unsigned int status, i;
		const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
		unsigned int reg_offset = gpudev->reg_offsets[offset];
		u64 ts1, ts2;

		adreno_writereg(adreno_dev, offset, val);

		if (!gmu_core_isenabled(KGSL_DEVICE(adreno_dev)))
		return 0;

		ts1 = gpudev->read_alwayson(adreno_dev);
		for (i = 0; i < GMU_CORE_LONG_WAKEUP_RETRY_LIMIT; i++) {
		/*
		* Make sure the previous register write is posted before
		@@ -3165,10 +3168,10 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,
		return 0;

		if (i == GMU_CORE_LONG_WAKEUP_RETRY_LIMIT) {
		ts2 = gpudev->read_alwayson(adreno_dev);
		dev_err(adreno_dev->dev.dev,
		"Timed out waiting %d usecs to write fenced register 0x%x\n",
		i * GMU_CORE_WAKEUP_DELAY_US,
		reg_offset);
		"Timed out waiting %d usecs to write fenced register 0x%x, timestamps: %llx %llx\n",
		i * GMU_CORE_WAKEUP_DELAY_US, reg_offset, ts1, ts2);
		return -ETIMEDOUT;
		}