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Commit 68481a7e authored by Krishna Reddy's avatar Krishna Reddy Committed by Ulf Hansson
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mmc: tegra: Mark 64 bit dma broken on Tegra186 



SDHCI controllers on Tegra186 support 40 bit addressing.
IOVA addresses are 48-bit wide on Tegra186.
SDHCI host common code sets dma mask as either 32-bit or 64-bit.
To avoid access issues when SMMU is enabled, disable 64-bit dma.

Signed-off-by: default avatarKrishna Reddy <vdumpa@nvidia.com>
Tested-by: default avatarThierry Reding <treding@nvidia.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent faf73fa1

drivers/mmc/host/sdhci-tegra.c

+9 −1
Original line number Diff line number Diff line
@@ -422,7 +422,15 @@ static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 
		  SDHCI_QUIRK_NO_HISPD_BIT |

		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |

		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,

	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,

	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |

		   /* SDHCI controllers on Tegra186 support 40-bit addressing.

		    * IOVA addresses are 48-bit wide on Tegra186.

		    * With 64-bit dma mask used for SDHCI, accesses can

		    * be broken. Disable 64-bit dma, which would fall back

		    * to 32-bit dma mask. Ideally 40-bit dma mask would work,

		    * But it is not supported as of now.

		    */

		   SDHCI_QUIRK2_BROKEN_64_BIT_DMA,

	.ops  = &tegra114_sdhci_ops,

};