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Commit 67affb78 authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Stephen Boyd
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clk: uniphier: fix DAPLL2 clock rate of Pro5 



The parent of DAPLL2 should be DAPLL1.  Fix the clock connection.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 3a5dfa7d

drivers/clk/uniphier/clk-uniphier-sys.c

+1 −1
Original line number Diff line number Diff line
@@ -123,7 +123,7 @@ const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = { 
const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {

	UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1),		/* 2400 MHz */

	UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1),	/* 2560 MHz */

	UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125),	/* 2949.12 MHz */

	UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125),	/* 2949.12 MHz */

	UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),

	UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),

	UNIPHIER_PRO5_SYS_CLK_NAND(2),