Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 676b4087 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: convert from number of lanes to lane bits on vega10 



We need a mask.

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewws-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9c2cc3a1

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

+5 −5
Original line number Diff line number Diff line
@@ -1170,12 +1170,12 @@ static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) 
					bios_pcie_table->entries[i].gen_speed;



		if (data->registry_data.pcieLaneOverride)

			pcie_table->pcie_lane[i] =

					data->registry_data.pcieLaneOverride;

			pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(

					data->registry_data.pcieLaneOverride);

		else

			pcie_table->pcie_lane[i] =

					bios_pcie_table->entries[i].lane_width;



			pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(

							bios_pcie_table->entries[i].lane_width);

		printk("pcie_table->pcie_lane[%d] is %d  %d\n", i, pcie_table->pcie_lane[i], bios_pcie_table->entries[i].lane_width);

		if (data->registry_data.pcieClockOverride)

			pcie_table->lclk[i] =

					data->registry_data.pcieClockOverride;