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Commit 67527bcb authored by Andre Przywara's avatar Andre Przywara Committed by Greg Kroah-Hartman
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net: axienet: Wrap DMA pointer writes to prepare for 64 bit 



[ Upstream commit 6a00d0dd3fcfa2ef200973479fbeee62f3681130 ]

Newer versions of the Xilink DMA IP support busses with more than 32
address bits, by introducing an MSB word for the registers holding DMA
pointers (tail/current, RX/TX descriptor addresses).
On IP configured for more than 32 bits, it is also *required* to write
both words, to let the IP recognise this as a start condition for an
MM2S request, for instance.

Wrap the DMA pointer writes with a separate function, to add this
functionality later. For now we stick to the lower 32 bits.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Stable-dep-of: 9ff2f816e2aa ("net: axienet: Fix register defines comment description")
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 29782285

drivers/net/ethernet/xilinx/xilinx_axienet_main.c

+16 −10
Original line number Diff line number Diff line
@@ -148,6 +148,12 @@ static inline void axienet_dma_out32(struct axienet_local *lp, 
	iowrite32(value, lp->dma_regs + reg);

}



static void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,

				 dma_addr_t addr)

{

	axienet_dma_out32(lp, reg, lower_32_bits(addr));

}



/**

 * axienet_dma_bd_release - Release buffer descriptor rings

 * @ndev:	Pointer to the net_device structure
@@ -286,18 +292,18 @@ static int axienet_dma_bd_init(struct net_device *ndev) 
	/* Populate the tail pointer and bring the Rx Axi DMA engine out of

	 * halted state. This will make the Rx side ready for reception.

	 */

	axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);

	axienet_dma_out_addr(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);

	cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);

	axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,

			  cr | XAXIDMA_CR_RUNSTOP_MASK);

	axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +

	axienet_dma_out_addr(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +

			     (sizeof(*lp->rx_bd_v) * (lp->rx_bd_num - 1)));



	/* Write to the RS (Run-stop) bit in the Tx channel control register.

	 * Tx channel is now ready to run. But only after we write to the

	 * tail pointer register that the Tx channel will start transmitting.

	 */

	axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);

	axienet_dma_out_addr(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);

	cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);

	axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,

			  cr | XAXIDMA_CR_RUNSTOP_MASK);
@@ -758,7 +764,7 @@ axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 


	tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;

	/* Start the transfer */

	axienet_dma_out32(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p);

	axienet_dma_out_addr(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p);

	if (++lp->tx_bd_tail >= lp->tx_bd_num)

		lp->tx_bd_tail = 0;
@@ -850,7 +856,7 @@ static void axienet_recv(struct net_device *ndev) 
	ndev->stats.rx_bytes += size;



	if (tail_p)

		axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p);

		axienet_dma_out_addr(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p);

}



/**
@@ -1683,18 +1689,18 @@ static void axienet_dma_err_handler(struct work_struct *work) 
	/* Populate the tail pointer and bring the Rx Axi DMA engine out of

	 * halted state. This will make the Rx side ready for reception.

	 */

	axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);

	axienet_dma_out_addr(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);

	cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);

	axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,

			  cr | XAXIDMA_CR_RUNSTOP_MASK);

	axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +

	axienet_dma_out_addr(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +

			     (sizeof(*lp->rx_bd_v) * (lp->rx_bd_num - 1)));



	/* Write to the RS (Run-stop) bit in the Tx channel control register.

	 * Tx channel is now ready to run. But only after we write to the

	 * tail pointer register that the Tx channel will start transmitting

	 */

	axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);

	axienet_dma_out_addr(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);

	cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);

	axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,

			  cr | XAXIDMA_CR_RUNSTOP_MASK);