Commit 672e60b7 authored Nov 18, 2018 by Heiko Stuebner

ARM: dts: rockchip: Remove @0 from the veyron memory node



The Coreboot version on veyron ChromeOS devices seems to ignore
memory@0 nodes when updating the available memory and instead
inserts another memory node without the address.

This leads to 4GB systems only ever be using 2GB as the memory@0
node takes precedence. So remove the @0 for veyron devices.

Fixes: 0b639b81 ("ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards")
Cc: stable@vger.kernel.org
Reported-by: Heikki Lindholm <holin@iki.fi>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

parent 65102238

arch/arm/boot/dts/rk3288-veyron.dtsi

+5 −1

Original line number	Diff line number	Diff line
		@@ -10,7 +10,11 @@
		#include "rk3288.dtsi"

		/ {
		memory@0 {
		/*
		* The default coreboot on veyron devices ignores memory@0 nodes
		* and would instead create another memory node.
		*/
		memory {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
		};