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Commit 66d043d4 authored by Alok Chauhan's avatar Alok Chauhan
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msm: camera: cdm: corrected submit bl logic 



CDM driver check for available bl fifo slots before
submitting to HW. If no free slots available then
it wait for CDM HW to process all the BLs and return
available slots.

CDM driver was incorrectly calculating the available bl
slots and causing bl fifo overflow.

Corrected the sequence in wait for bl fifo logic.

CRs-Fixed: 2837583
Change-Id: I2861f8c66822e0739f0546eaf153d8e2af0caefe
Signed-off-by: default avatarAlok Chauhan <alokc@codeaurora.org>
parent d12abfb4

drivers/cam_cdm/cam_cdm_hw_core.c

+7 −8
Original line number Diff line number Diff line
@@ -586,13 +586,9 @@ int cam_hw_cdm_wait_for_bl_fifo( 
				pending_bl);

			break;

		}

		if (bl_count < (available_bl_slots - 1)) {

			CAM_DBG(CAM_CDM,

				"BL slot available_cnt=%d requested=%d",

				(available_bl_slots - 1), bl_count);

				rc = available_bl_slots - 1;

				break;

		} else if (0 == (available_bl_slots - 1)) {

		if (0 == (available_bl_slots - 1)) {

			reinit_completion(&core->bl_fifo[fifo_idx].bl_complete);



			rc = cam_hw_cdm_enable_bl_done_irq(cdm_hw,

				true, fifo_idx);

			if (rc) {
@@ -619,7 +615,10 @@ int cam_hw_cdm_wait_for_bl_fifo( 
			rc = 1;

			CAM_DBG(CAM_CDM, "CDM HW is ready for data");

		} else {

			rc = (bl_count - (available_bl_slots - 1));

			CAM_DBG(CAM_CDM,

				"BL slot available_cnt=%d requested=%d",

				(available_bl_slots - 1), bl_count);

			rc = available_bl_slots - 1;

			break;

		}

	} while (1);