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Commit 66aa6c35 authored by Sandeep Singh's avatar Sandeep Singh
Browse files

ARM: dts: msm: Enable icnss node for blair 

Enable icnss node and update regulator config
for blair.

Change-Id: I101921c66deab6378967bba258779303e6ce0d25
parent fa462f63

qcom/blair-atp.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -204,3 +204,14 @@ 
	vdd-supply = <&L16A>;

	core-supply = <&L22A>;

};



&icnss {

	vdd-cx-mx-supply = <&L4A>;

	vdd-1.8-xo-supply = <&L7A>;

	vdd-1.3-rfa-supply = <&L2E>;

	vdd-3.3-ch1-supply = <&L11E>;

	vdd-3.3-ch0-supply = <&L10E>;

	qcom,vdd-cx-mx-config = <640000 640000>;

	qcom,vdd-3.3-ch1-config = <3000000 3312000>;

	qcom,vdd-3.3-ch0-config = <3000000 3312000>;

};

qcom/blair.dtsi

+42 −32
Original line number Diff line number Diff line
@@ -3184,38 +3184,6 @@ 
		status = "ok";

	};



	icnss: qcom,icnss@C800000 {

		status = "disabled";

		compatible = "qcom,icnss";

		reg = <0xC800000 0x800000>,

		      <0xb0000000 0x10000>;

		reg-names = "membase", "smmu_iova_ipa";

		iommus = <&apps_smmu 0x80 0x1>;

		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,

			     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,

			     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,

			     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,

			     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,

			     <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,

			     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,

			     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,

			     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,

			     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,

			     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH /* CE10 */ >,

			     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH /* CE11 */ >;

		qcom,iommu-dma = "fastmap";

		qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";

		qcom,wlan-msa-fixed-region = <&pil_wlan_mem>;

		qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;

		qcom,iommu-geometry = <0xa0000000 0x10010000>;

		qcom,smp2p_map_wlan_1_in {

			interrupts-extended = <&smp2p_wlan_1_in 0 0>,

					      <&smp2p_wlan_1_in 1 0>;

			interrupt-names = "qcom,smp2p-force-fatal-error",

					  "qcom,smp2p-early-crash-ind";

		};

	};



	qcom,msm_gsi {

		compatible = "qcom,msm_gsi";

	};
@@ -3775,4 +3743,46 @@ 
	};

};



&soc {

	icnss: qcom,icnss@C800000 {

		compatible = "qcom,icnss";

		reg = <0xC800000 0x800000>,

		      <0xb0000000 0x10000>;

		reg-names = "membase", "smmu_iova_ipa";

		iommus = <&apps_smmu 0x80 0x1>;

		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,

			     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,

			     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,

			     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,

			     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,

			     <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,

			     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,

			     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,

			     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,

			     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,

			     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH /* CE10 */ >,

			     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH /* CE11 */ >;

		qcom,iommu-dma = "fastmap";

		qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";

		qcom,wlan-msa-fixed-region = <&pil_wlan_mem>;

		qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;

		qcom,iommu-geometry = <0xa0000000 0x10010000>;

		vdd-cx-mx-supply = <&L2E>;

		vdd-1.8-xo-supply = <&L16A>;

		vdd-1.3-rfa-supply = <&L2A>;

		vdd-3.3-ch1-supply = <&L21A>;

		vdd-3.3-ch0-supply = <&L23A>;

		qcom,vdd-cx-mx-config = <640000 640000>;

		qcom,vdd-3.3-ch1-config = <3000000 3312000>;

		qcom,vdd-3.3-ch0-config = <3000000 3312000>;

		qcom,smp2p_map_wlan_1_in {

			interrupts-extended = <&smp2p_wlan_1_in 0 0>,

					      <&smp2p_wlan_1_in 1 0>;

			interrupt-names = "qcom,smp2p-force-fatal-error",

					  "qcom,smp2p-early-crash-ind";

		};

	};



};



#include "msm-rdbg.dtsi"