Commit 668e84b2 authored Oct 21, 2014 by Sebastian Hesselbarth Committed by Ulf Hansson Nov 10, 2014

mmc: sdhci-pxav3: Respect MMC_DDR52 timing on uhs signaling



commit bb8175a8
  ("mmc: sdhci: clarify DDR timing mode between SD-UHS and eMMC")
added MMC_DDR52 as eMMC's DDR mode to be distinguished from SD-UHS.

While the differentation may be useful, pxav3 SDHCI controller lacks
a corresponding check in its custom .set_uhs_signaling callback for
MMC_DDR52. This patch adds a new switch case for MMC_TIMING_MMC_DDR52
to MMC_TIMING_UHS_DDR50 case.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

parent 6a686c31

drivers/mmc/host/sdhci-pxav3.c

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -211,6 +211,7 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
	case MMC_TIMING_UHS_SDR104:		case MMC_TIMING_UHS_SDR104:
	ctrl_2 \|= SDHCI_CTRL_UHS_SDR104 \| SDHCI_CTRL_VDD_180;		ctrl_2 \|= SDHCI_CTRL_UHS_SDR104 \| SDHCI_CTRL_VDD_180;
	break;		break;
			case MMC_TIMING_MMC_DDR52:
	case MMC_TIMING_UHS_DDR50:		case MMC_TIMING_UHS_DDR50:
	ctrl_2 \|= SDHCI_CTRL_UHS_DDR50 \| SDHCI_CTRL_VDD_180;		ctrl_2 \|= SDHCI_CTRL_UHS_DDR50 \| SDHCI_CTRL_VDD_180;
	break;		break;