Loading drivers/gpu/msm/adreno.c +4 −0 Original line number Diff line number Diff line Loading @@ -1239,6 +1239,8 @@ static int adreno_probe_llcc(struct adreno_device *adreno_dev, "Unable to get the GPU LLC slice: %d\n", ret); } adreno_dev->gpu_llc_slice_enable = true; /* Get the system cache slice descriptor for GPU pagetables */ adreno_dev->gpuhtw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); ret = PTR_ERR_OR_ZERO(adreno_dev->gpuhtw_llc_slice); Loading @@ -1253,6 +1255,8 @@ static int adreno_probe_llcc(struct adreno_device *adreno_dev, "Unable to get GPU HTW LLC slice: %d\n", ret); } adreno_dev->gpuhtw_llc_slice_enable = true; return 0; } Loading drivers/gpu/msm/adreno_a6xx.c +0 −3 Original line number Diff line number Diff line Loading @@ -2134,9 +2134,6 @@ int a6xx_probe_common(struct platform_device *pdev, adreno_dev->preempt.skipsaverestore = true; adreno_dev->preempt.usesgmem = true; adreno_dev->gpu_llc_slice_enable = true; adreno_dev->gpuhtw_llc_slice_enable = true; /* Set the GPU busy counter for frequency scaling */ adreno_dev->perfctr_pwr_lo = A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L; Loading drivers/gpu/msm/adreno_sysfs.c +4 −2 Original line number Diff line number Diff line Loading @@ -49,6 +49,7 @@ static unsigned int _ft_pagefault_policy_show(struct adreno_device *adreno_dev) static int _gpu_llc_slice_enable_store(struct adreno_device *adreno_dev, bool val) { if (!IS_ERR_OR_NULL(adreno_dev->gpu_llc_slice)) adreno_dev->gpu_llc_slice_enable = val; return 0; } Loading @@ -61,6 +62,7 @@ static bool _gpu_llc_slice_enable_show(struct adreno_device *adreno_dev) static int _gpuhtw_llc_slice_enable_store(struct adreno_device *adreno_dev, bool val) { if (!IS_ERR_OR_NULL(adreno_dev->gpuhtw_llc_slice)) adreno_dev->gpuhtw_llc_slice_enable = val; return 0; } Loading Loading
drivers/gpu/msm/adreno.c +4 −0 Original line number Diff line number Diff line Loading @@ -1239,6 +1239,8 @@ static int adreno_probe_llcc(struct adreno_device *adreno_dev, "Unable to get the GPU LLC slice: %d\n", ret); } adreno_dev->gpu_llc_slice_enable = true; /* Get the system cache slice descriptor for GPU pagetables */ adreno_dev->gpuhtw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); ret = PTR_ERR_OR_ZERO(adreno_dev->gpuhtw_llc_slice); Loading @@ -1253,6 +1255,8 @@ static int adreno_probe_llcc(struct adreno_device *adreno_dev, "Unable to get GPU HTW LLC slice: %d\n", ret); } adreno_dev->gpuhtw_llc_slice_enable = true; return 0; } Loading
drivers/gpu/msm/adreno_a6xx.c +0 −3 Original line number Diff line number Diff line Loading @@ -2134,9 +2134,6 @@ int a6xx_probe_common(struct platform_device *pdev, adreno_dev->preempt.skipsaverestore = true; adreno_dev->preempt.usesgmem = true; adreno_dev->gpu_llc_slice_enable = true; adreno_dev->gpuhtw_llc_slice_enable = true; /* Set the GPU busy counter for frequency scaling */ adreno_dev->perfctr_pwr_lo = A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L; Loading
drivers/gpu/msm/adreno_sysfs.c +4 −2 Original line number Diff line number Diff line Loading @@ -49,6 +49,7 @@ static unsigned int _ft_pagefault_policy_show(struct adreno_device *adreno_dev) static int _gpu_llc_slice_enable_store(struct adreno_device *adreno_dev, bool val) { if (!IS_ERR_OR_NULL(adreno_dev->gpu_llc_slice)) adreno_dev->gpu_llc_slice_enable = val; return 0; } Loading @@ -61,6 +62,7 @@ static bool _gpu_llc_slice_enable_show(struct adreno_device *adreno_dev) static int _gpuhtw_llc_slice_enable_store(struct adreno_device *adreno_dev, bool val) { if (!IS_ERR_OR_NULL(adreno_dev->gpuhtw_llc_slice)) adreno_dev->gpuhtw_llc_slice_enable = val; return 0; } Loading