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Commit 66579ee1 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Greg Kroah-Hartman
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ARM: dts: imx: Align L2 cache-controller nodename with dtschema 



[ Upstream commit 69cc1502a87f5ed12e27dbe5fe2bfdd5540826c7 ]

Fix dtschema validator warnings like:
    l2-cache@a02000: $nodename:0:
        'l2-cache@a02000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
Stable-dep-of: ee70b908f77a ("ARM: dts: nxp/imx6sll: fix wrong property name in usbphy node")
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 3b454fb9

arch/arm/boot/dts/imx35.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ 
		interrupt-parent = <&avic>;

		ranges;



		L2: l2-cache@30000000 {

		L2: cache-controller@30000000 {

			compatible = "arm,l210-cache";

			reg = <0x30000000 0x1000>;

			cache-unified;

arch/arm/boot/dts/imx6qdl.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -255,7 +255,7 @@ 
			interrupt-parent = <&intc>;

		};



		L2: l2-cache@a02000 {

		L2: cache-controller@a02000 {

			compatible = "arm,pl310-cache";

			reg = <0x00a02000 0x1000>;

			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;

arch/arm/boot/dts/imx6sl.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -136,7 +136,7 @@ 
			interrupt-parent = <&intc>;

		};



		L2: l2-cache@a02000 {

		L2: cache-controller@a02000 {

			compatible = "arm,pl310-cache";

			reg = <0x00a02000 0x1000>;

			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;

arch/arm/boot/dts/imx6sll.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ 
			interrupt-parent = <&intc>;

		};



		L2: l2-cache@a02000 {

		L2: cache-controller@a02000 {

			compatible = "arm,pl310-cache";

			reg = <0x00a02000 0x1000>;

			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;

arch/arm/boot/dts/imx6sx.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -187,7 +187,7 @@ 
			interrupt-parent = <&intc>;

		};



		L2: l2-cache@a02000 {

		L2: cache-controller@a02000 {

			compatible = "arm,pl310-cache";

			reg = <0x00a02000 0x1000>;

			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;