Loading include/dt-bindings/clock/rk3228-cru.h +1 −0 Original line number Diff line number Diff line Loading @@ -73,6 +73,7 @@ #define SCLK_WIFI 141 #define SCLK_OTGPHY0 142 #define SCLK_OTGPHY1 143 #define SCLK_HDMI_PHY 144 /* dclk gates */ #define DCLK_VOP 190 Loading include/dt-bindings/clock/rk3328-cru.h +1 −0 Original line number Diff line number Diff line Loading @@ -173,6 +173,7 @@ #define PCLK_DCF 233 #define PCLK_SARADC 234 #define PCLK_ACODECPHY 235 #define PCLK_WDT 236 /* hclk gates */ #define HCLK_PERI 308 Loading Loading
include/dt-bindings/clock/rk3228-cru.h +1 −0 Original line number Diff line number Diff line Loading @@ -73,6 +73,7 @@ #define SCLK_WIFI 141 #define SCLK_OTGPHY0 142 #define SCLK_OTGPHY1 143 #define SCLK_HDMI_PHY 144 /* dclk gates */ #define DCLK_VOP 190 Loading
include/dt-bindings/clock/rk3328-cru.h +1 −0 Original line number Diff line number Diff line Loading @@ -173,6 +173,7 @@ #define PCLK_DCF 233 #define PCLK_SARADC 234 #define PCLK_ACODECPHY 235 #define PCLK_WDT 236 /* hclk gates */ #define HCLK_PERI 308 Loading