Loading qcom/sdxnightjar-pinctrl.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -4,7 +4,7 @@ tlmm_pinmux: pinctrl@1000000 { compatible = "qcom,sdxnightjar-pinctrl"; reg = <0x1000000 0x300000>; interrupts = <0 208 0>; interrupts = <0 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; Loading qcom/sdxnightjar.dtsi +5 −4 Original line number Diff line number Diff line Loading @@ -589,7 +589,7 @@ blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78af000 0x200>; interrupts = <0 107 0>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; Loading @@ -599,7 +599,7 @@ blsp1_uart2: serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78b0000 0x200>; interrupts = <0 108 0>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; Loading @@ -609,7 +609,7 @@ blsp1_uart3: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78b1000 0x200>; interrupts = <0 109 0>; interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; Loading @@ -627,7 +627,8 @@ compatible = "qcom,msm-watchdog"; reg = <0xb017000 0x1000>; reg-names = "wdt-base"; interrupts = <1 3 0>, <1 2 0>; interrupts = <1 3 IRQ_TYPE_EDGE_RISING>, <1 2 IRQ_TYPE_EDGE_RISING>; qcom,bark-time = <11000>; qcom,pet-time = <10000>; }; Loading Loading
qcom/sdxnightjar-pinctrl.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -4,7 +4,7 @@ tlmm_pinmux: pinctrl@1000000 { compatible = "qcom,sdxnightjar-pinctrl"; reg = <0x1000000 0x300000>; interrupts = <0 208 0>; interrupts = <0 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; Loading
qcom/sdxnightjar.dtsi +5 −4 Original line number Diff line number Diff line Loading @@ -589,7 +589,7 @@ blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78af000 0x200>; interrupts = <0 107 0>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; Loading @@ -599,7 +599,7 @@ blsp1_uart2: serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78b0000 0x200>; interrupts = <0 108 0>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; Loading @@ -609,7 +609,7 @@ blsp1_uart3: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78b1000 0x200>; interrupts = <0 109 0>; interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; Loading @@ -627,7 +627,8 @@ compatible = "qcom,msm-watchdog"; reg = <0xb017000 0x1000>; reg-names = "wdt-base"; interrupts = <1 3 0>, <1 2 0>; interrupts = <1 3 IRQ_TYPE_EDGE_RISING>, <1 2 IRQ_TYPE_EDGE_RISING>; qcom,bark-time = <11000>; qcom,pet-time = <10000>; }; Loading