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Unverified Commit 65bf2d54 authored by Paul Kocialkowski's avatar Paul Kocialkowski Committed by Maxime Ripard
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drm/sun4i: tcon: Support an active-low DE signal with RGB interface 



Some panels need an active-low data enable (DE) signal for the RGB
interface. This requires flipping a bit in the TCON0 polarity register
when setting up the mode for the RGB interface.

Match the associated bus flag and use it to set the polarity inversion
bit for the DE signal when required.

Signed-off-by: default avatarPaul Kocialkowski <contact@paulk.fr>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181107181843.27628-4-contact@paulk.fr
parent 4843c9a2

drivers/gpu/drm/sun4i/sun4i_tcon.c

+6 −1
Original line number Diff line number Diff line
@@ -543,6 +543,9 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, 
	if (mode->flags & DRM_MODE_FLAG_PVSYNC)

		val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;



	if (display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)

		val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;



	/*

	 * On A20 and similar SoCs, the only way to achieve Positive Edge

	 * (Rising Edge), is setting dclk clock phase to 2/3(240°).
@@ -565,7 +568,9 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, 
		clk_set_phase(tcon->dclk, 0);



	regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,

			   SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,

			   SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |

			   SUN4I_TCON0_IO_POL_VSYNC_POSITIVE |

			   SUN4I_TCON0_IO_POL_DE_NEGATIVE,

			   val);



	/* Map output pins to channel 0 */

drivers/gpu/drm/sun4i/sun4i_tcon.h

+1 −0
Original line number Diff line number Diff line
@@ -116,6 +116,7 @@ 


#define SUN4I_TCON0_IO_POL_REG			0x88

#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase)		((phase & 3) << 28)

#define SUN4I_TCON0_IO_POL_DE_NEGATIVE			BIT(27)

#define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE		BIT(25)

#define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE		BIT(24)