Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6575b1d4 authored by Leonid Yegoshin's avatar Leonid Yegoshin Committed by Ralf Baechle
Browse files

MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions 



Detect if the core supports unique exception codes for the
Read-Inhibit and Execute-Inhibit exceptions and set the
option accordingly. The RI/XI exception support is detected
by setting the 27th bit (IEC) of the PageGrain C0 register
and reading back the value of that register to verify the
bit is enabled.

Signed-off-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7340/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 5890f70f

arch/mips/include/asm/mipsregs.h

+1 −0
Original line number Diff line number Diff line
@@ -265,6 +265,7 @@ 
#define PG_XIE		(_ULCAST_(1) <<	 30)

#define PG_ELPA		(_ULCAST_(1) <<	 29)

#define PG_ESP		(_ULCAST_(1) <<	 28)

#define PG_IEC		(_ULCAST_(1) <<  27)



/*

 * R4x00 interrupt enable / cause bits

arch/mips/kernel/cpu-probe.c

+9 −0
Original line number Diff line number Diff line
@@ -438,6 +438,15 @@ static void decode_configs(struct cpuinfo_mips *c) 


	mips_probe_watch_registers(c);



	if (cpu_has_rixi) {

		/* Enable the RIXI exceptions */

		write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);

		back_to_back_c0_hazard();

		/* Verify the IEC bit is set */

		if (read_c0_pagegrain() & PG_IEC)

			c->options |= MIPS_CPU_RIXIEX;

	}



#ifndef CONFIG_MIPS_CPS

	if (cpu_has_mips_r2) {

		c->core = get_ebase_cpunum();