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Commit 6525771f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-5.3-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC updates from Vineet Gupta:

 - support for Edge Triggered IRQs in ARC IDU intc

 - other fixes here and there

* tag 'arc-5.3-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  arc: prefer __section from compiler_attributes.h
  dt-bindings: IDU-intc: Add support for edge-triggered interrupts
  dt-bindings: IDU-intc: Clean up documentation
  ARCv2: IDU-intc: Add support for edge-triggered interrupts
  ARC: unwind: Mark expected switch fall-throughs
  ARC: [plat-hsdk]: allow to switch between AXI DMAC port configurations
  ARC: fix typo in setup_dma_ops log message
  ARCv2: entry: early return from exception need not clear U & DE bits
parents 8d645408 2f029413

Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt

+20 −10
Original line number Diff line number Diff line 
* ARC-HS Interrupt Distribution Unit



  This optional 2nd level interrupt controller can be used in SMP configurations for

  dynamic IRQ routing, load balancing of common/external IRQs towards core intc.

  This optional 2nd level interrupt controller can be used in SMP configurations

  for dynamic IRQ routing, load balancing of common/external IRQs towards core

  intc.



Properties:



- compatible: "snps,archs-idu-intc"

- interrupt-controller: This is an interrupt controller.

- #interrupt-cells: Must be <1>.



  Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N

  of the particular interrupt line of IDU corresponds to the line N+24 of the

  core interrupt controller.



  intc accessed via the special ARC AUX register interface, hence "reg" property

  is not specified.

- #interrupt-cells: Must be <1> or <2>.



  Value of the first cell specifies the "common" IRQ from peripheral to IDU.

  Number N of the particular interrupt line of IDU corresponds to the line N+24

  of the core interrupt controller.



  The (optional) second cell specifies any of the following flags:

    - bits[3:0] trigger type and level flags

        1 = low-to-high edge triggered

        2 = NOT SUPPORTED (high-to-low edge triggered)

        4 = active high level-sensitive <<< DEFAULT

        8 = NOT SUPPORTED (active low level-sensitive)

  When no second cell is specified, the interrupt is assumed to be level

  sensitive.



  The interrupt controller is accessed via the special ARC AUX register

  interface, hence "reg" property is not specified.



Example:

	core_intc: core-interrupt-controller {

arch/arc/boot/dts/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -12,3 +12,6 @@ dtb-y := $(builtindtb-y).dtb 
# for CONFIG_OF_ALL_DTBS test

dtstree	:= $(srctree)/$(src)

dtb-	:= $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))



# board-specific dtc flags

DTC_FLAGS_hsdk += --pad 20

arch/arc/include/asm/entry-arcv2.h

+1 −1
Original line number Diff line number Diff line
@@ -256,7 +256,7 @@ 


.macro FAKE_RET_FROM_EXCPN

	lr      r9, [status32]

	bic     r9, r9, (STATUS_U_MASK|STATUS_DE_MASK|STATUS_AE_MASK)

	bic     r9, r9, STATUS_AE_MASK

	or      r9, r9, STATUS_IE_MASK

	kflag   r9

.endm

arch/arc/include/asm/linkage.h

+4 −4
Original line number Diff line number Diff line
@@ -62,15 +62,15 @@ 
#else	/* !__ASSEMBLY__ */



#ifdef CONFIG_ARC_HAS_ICCM

#define __arcfp_code __attribute__((__section__(".text.arcfp")))

#define __arcfp_code __section(.text.arcfp)

#else

#define __arcfp_code __attribute__((__section__(".text")))

#define __arcfp_code __section(.text)

#endif



#ifdef CONFIG_ARC_HAS_DCCM

#define __arcfp_data __attribute__((__section__(".data.arcfp")))

#define __arcfp_data __section(.data.arcfp)

#else

#define __arcfp_data __attribute__((__section__(".data")))

#define __arcfp_data __section(.data)

#endif



#endif /* __ASSEMBLY__ */

arch/arc/include/asm/mach_desc.h

+1 −2
Original line number Diff line number Diff line
@@ -53,8 +53,7 @@ extern const struct machine_desc __arch_info_begin[], __arch_info_end[]; 
 */

#define MACHINE_START(_type, _name)			\

static const struct machine_desc __mach_desc_##_type	\

__used							\

__attribute__((__section__(".arch.info.init"))) = {	\

__used __section(.arch.info.init) = {			\

	.name		= _name,



#define MACHINE_END				\