Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6501a771 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: init RSMU and UMC ip base address for vega20 



the driver needs to program RSMU and UMC registers to
support vega20 RAS feature

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarDennis Li <dennis.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7af25d5b

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −0
Original line number Diff line number Diff line
@@ -752,6 +752,8 @@ enum amd_hw_ip_block_type { 
	NBIF_HWIP,

	THM_HWIP,

	CLK_HWIP,

	UMC_HWIP,

	RSMU_HWIP,

	MAX_HWIP

};

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

+2 −0
Original line number Diff line number Diff line
@@ -50,6 +50,8 @@ int vega20_reg_base_init(struct amdgpu_device *adev) 
		adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));

		adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));

		adev->reg_offset[RSMU_HWIP][i] = (uint32_t *)(&(RSMU_BASE.instance[i]));

	}

	return 0;

}