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Commit 64d26f8c authored by Abel Vesa's avatar Abel Vesa Committed by Shawn Guo
Browse files

arm64: dts: imx8mq: Add the opp table and cores opp properties 

Add the 0.8GHz and 1GHz opps. According to the datasheet:
https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf


section 3.1.3 Operating ranges.

The 0.8GHz opp runs in nominal mode with the regulator set to 0.9V.
The 1GHz runs in overdrive mode with the regulator set to 1V.

Signed-off-by: default avatarAbel Vesa <abel.vesa@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 9b87ebb1

arch/arm64/boot/dts/freescale/imx8mq.dtsi

+23 −0
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ 
			clocks = <&clk IMX8MQ_CLK_ARM>;

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			operating-points-v2 = <&a53_opp_table>;

		};



		A53_1: cpu@1 {
@@ -101,6 +102,7 @@ 
			clocks = <&clk IMX8MQ_CLK_ARM>;

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			operating-points-v2 = <&a53_opp_table>;

		};



		A53_2: cpu@2 {
@@ -111,6 +113,7 @@ 
			clocks = <&clk IMX8MQ_CLK_ARM>;

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			operating-points-v2 = <&a53_opp_table>;

		};



		A53_3: cpu@3 {
@@ -121,6 +124,7 @@ 
			clocks = <&clk IMX8MQ_CLK_ARM>;

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			operating-points-v2 = <&a53_opp_table>;

		};



		A53_L2: l2-cache0 {
@@ -674,6 +678,25 @@ 
			status = "disabled";

		};





		a53_opp_table: opp-table {

			compatible = "operating-points-v2";

			opp-shared;



			opp-800000000 {

				opp-hz = /bits/ 64 <800000000>;

				opp-microvolt = <900000>;

				clock-latency-ns = <150000>;

			};



			opp-1000000000 {

				opp-hz = /bits/ 64 <1000000000>;

				opp-microvolt = <1000000>;

				clock-latency-ns = <150000>;

				opp-suspend;

			};

		};



		gic: interrupt-controller@38800000 {

			compatible = "arm,gic-v3";

			reg = <0x38800000 0x10000>,	/* GIC Dist */