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Commit 643e7225 authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update KnightsLanding events to v9 



Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent efc351f1

tools/perf/pmu-events/arch/x86/knightslanding/cache.json

+333 −333
Original line number Diff line number Diff line
@@ -121,7 +121,7 @@ 
        "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {
@@ -187,7 +187,7 @@ 
        "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts any Read request  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts any Read request  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {
@@ -253,7 +253,7 @@ 
        "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {
@@ -319,7 +319,7 @@ 
        "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts Demand cacheable data write requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts Demand cacheable data write requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {
@@ -385,7 +385,7 @@ 
        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {
@@ -451,7 +451,7 @@ 
        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {
@@ -539,7 +539,7 @@ 
        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {
@@ -605,7 +605,7 @@ 
        "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {
@@ -682,7 +682,7 @@ 
        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {
@@ -748,7 +748,7 @@ 
        "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {
@@ -869,7 +869,7 @@ 
        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {
@@ -935,7 +935,7 @@ 
        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {
@@ -1067,7 +1067,7 @@ 
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {
@@ -1133,7 +1133,7 @@ 
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {
@@ -1199,7 +1199,7 @@ 
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",

        "MSRIndex": "0x1a6",

        "SampleAfterValue": "100007",

        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ",

        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",

        "Offcore": "1"

    },

    {

tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json

+6 −9
Original line number Diff line number Diff line
@@ -272,7 +272,6 @@ 
    },

    {

        "PublicDescription": "This event counts the number of instructions that retire.  For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires.  The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.",

        "EventCode": "0x00",

        "Counter": "Fixed counter 1",

        "UMask": "0x1",

        "EventName": "INST_RETIRED.ANY",
@@ -296,8 +295,7 @@ 
        "BriefDescription": "Counts the number of unhalted reference clock cycles"

    },

    {

        "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter\r\n",

        "EventCode": "0x00",

        "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter",

        "Counter": "Fixed counter 2",

        "UMask": "0x2",

        "EventName": "CPU_CLK_UNHALTED.THREAD",
@@ -305,7 +303,6 @@ 
        "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles"

    },

    {

        "EventCode": "0x00",

        "Counter": "Fixed counter 3",

        "UMask": "0x3",

        "EventName": "CPU_CLK_UNHALTED.REF_TSC",

tools/perf/pmu-events/arch/x86/knightslanding/memory.json

+134 −134

File changed.

Contains only whitespace changes.

tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json

+1 −1

File changed.

Contains only whitespace changes.