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Commit 640bdb1f authored by Alaa Hleihel's avatar Alaa Hleihel Committed by Saeed Mahameed
Browse files

net/mlx5: DR, Allow matching on vport based on vhca_id 



In case source_eswitch_owner_vhca_id is given as a match,
the source_vport (vhca_id) will be set in case vhca_id_valid.

This will allow matching on peer vports, vports that belong
to the other pf.

Fixes: 26d688e3 ("net/mlx5: DR, Add Steering entry (STE) utilities")
Signed-off-by: default avatarAlaa Hleihel <alaa@mellanox.com>
Signed-off-by: default avatarAlex Vesker <valex@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent 48cbde4b

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c

+1 −2
Original line number Diff line number Diff line
@@ -230,8 +230,7 @@ static int dr_matcher_set_ste_builders(struct mlx5dr_matcher *matcher, 
		    (dmn->type == MLX5DR_DOMAIN_TYPE_FDB ||

		     dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX)) {

			ret = mlx5dr_ste_build_src_gvmi_qpn(&sb[idx++], &mask,

							    &dmn->info.caps,

							    inner, rx);

							    dmn, inner, rx);

			if (ret)

				return ret;

		}

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c

+32 −4
Original line number Diff line number Diff line
@@ -837,6 +837,8 @@ static void dr_ste_copy_mask_misc(char *mask, struct mlx5dr_match_misc *spec) 
	spec->source_sqn = MLX5_GET(fte_match_set_misc, mask, source_sqn);



	spec->source_port = MLX5_GET(fte_match_set_misc, mask, source_port);

	spec->source_eswitch_owner_vhca_id = MLX5_GET(fte_match_set_misc, mask,

						      source_eswitch_owner_vhca_id);



	spec->outer_second_prio = MLX5_GET(fte_match_set_misc, mask, outer_second_prio);

	spec->outer_second_cfi = MLX5_GET(fte_match_set_misc, mask, outer_second_cfi);
@@ -2250,11 +2252,18 @@ static int dr_ste_build_src_gvmi_qpn_bit_mask(struct mlx5dr_match_param *value, 
{

	struct mlx5dr_match_misc *misc_mask = &value->misc;



	if (misc_mask->source_port != 0xffff)

	/* Partial misc source_port is not supported */

	if (misc_mask->source_port && misc_mask->source_port != 0xffff)

		return -EINVAL;



	/* Partial misc source_eswitch_owner_vhca_id is not supported */

	if (misc_mask->source_eswitch_owner_vhca_id &&

	    misc_mask->source_eswitch_owner_vhca_id != 0xffff)

		return -EINVAL;



	DR_STE_SET_MASK(src_gvmi_qp, bit_mask, source_gvmi, misc_mask, source_port);

	DR_STE_SET_MASK(src_gvmi_qp, bit_mask, source_qp, misc_mask, source_sqn);

	misc_mask->source_eswitch_owner_vhca_id = 0;



	return 0;

}
@@ -2266,17 +2275,33 @@ static int dr_ste_build_src_gvmi_qpn_tag(struct mlx5dr_match_param *value, 
	struct dr_hw_ste_format *hw_ste = (struct dr_hw_ste_format *)hw_ste_p;

	struct mlx5dr_match_misc *misc = &value->misc;

	struct mlx5dr_cmd_vport_cap *vport_cap;

	struct mlx5dr_domain *dmn = sb->dmn;

	struct mlx5dr_cmd_caps *caps;

	u8 *tag = hw_ste->tag;



	DR_STE_SET_TAG(src_gvmi_qp, tag, source_qp, misc, source_sqn);



	vport_cap = mlx5dr_get_vport_cap(sb->caps, misc->source_port);

	if (sb->vhca_id_valid) {

		/* Find port GVMI based on the eswitch_owner_vhca_id */

		if (misc->source_eswitch_owner_vhca_id == dmn->info.caps.gvmi)

			caps = &dmn->info.caps;

		else if (dmn->peer_dmn && (misc->source_eswitch_owner_vhca_id ==

					   dmn->peer_dmn->info.caps.gvmi))

			caps = &dmn->peer_dmn->info.caps;

		else

			return -EINVAL;

	} else {

		caps = &dmn->info.caps;

	}



	vport_cap = mlx5dr_get_vport_cap(caps, misc->source_port);

	if (!vport_cap)

		return -EINVAL;



	if (vport_cap->vport_gvmi)

		MLX5_SET(ste_src_gvmi_qp, tag, source_gvmi, vport_cap->vport_gvmi);



	misc->source_eswitch_owner_vhca_id = 0;

	misc->source_port = 0;



	return 0;
@@ -2284,17 +2309,20 @@ static int dr_ste_build_src_gvmi_qpn_tag(struct mlx5dr_match_param *value, 


int mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_build *sb,

				  struct mlx5dr_match_param *mask,

				  struct mlx5dr_cmd_caps *caps,

				  struct mlx5dr_domain *dmn,

				  bool inner, bool rx)

{

	int ret;



	/* Set vhca_id_valid before we reset source_eswitch_owner_vhca_id */

	sb->vhca_id_valid = mask->misc.source_eswitch_owner_vhca_id;



	ret = dr_ste_build_src_gvmi_qpn_bit_mask(mask, sb->bit_mask);

	if (ret)

		return ret;



	sb->rx = rx;

	sb->caps = caps;

	sb->dmn = dmn;

	sb->inner = inner;

	sb->lu_type = MLX5DR_STE_LU_TYPE_SRC_GVMI_AND_QP;

	sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask);

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h

+4 −2
Original line number Diff line number Diff line
@@ -180,6 +180,8 @@ void mlx5dr_send_fill_and_append_ste_send_info(struct mlx5dr_ste *ste, u16 size, 
struct mlx5dr_ste_build {

	u8 inner:1;

	u8 rx:1;

	u8 vhca_id_valid:1;

	struct mlx5dr_domain *dmn;

	struct mlx5dr_cmd_caps *caps;

	u8 lu_type;

	u16 byte_mask;
@@ -331,7 +333,7 @@ void mlx5dr_ste_build_register_1(struct mlx5dr_ste_build *sb, 
				 bool inner, bool rx);

int mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_build *sb,

				  struct mlx5dr_match_param *mask,

				  struct mlx5dr_cmd_caps *caps,

				  struct mlx5dr_domain *dmn,

				  bool inner, bool rx);

void mlx5dr_ste_build_empty_always_hit(struct mlx5dr_ste_build *sb, bool rx);
@@ -453,7 +455,7 @@ struct mlx5dr_match_misc { 
	u32 gre_c_present:1;

	/* Source port.;0xffff determines wire port */

	u32 source_port:16;

	u32 reserved_auto2:16;

	u32 source_eswitch_owner_vhca_id:16;

	/* VLAN ID of first VLAN tag the inner header of the incoming packet.

	 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1

	 */