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Commit 63a58ef9 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "defconfig: sdxlemur: enable QCOM PCIe drivers"

parents 1807fa03 e2ad3554

arch/arm/configs/vendor/sdxlemur.config

+1 −0
Original line number Diff line number Diff line
@@ -62,3 +62,4 @@ CONFIG_QTI_RPM_STATS_LOG=y 
CONFIG_QTI_DDR_STATS_LOG=y

CONFIG_QCOM_SOC_SLEEP_STATS=y

CONFIG_QCOM_PDC=y

CONFIG_PCI_MSM=y

arch/arm/mach-qcom/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -49,7 +49,9 @@ config ARCH_SDXLEMUR 
	select CPU_V7

	select ARM_GIC

	select HAVE_ARM_ARCH_TIMER

	select HAVE_PCI

	select MSM_CORTEX_A7

	select PCI

	select PINCTRL

	select QCOM_SCM if SMP

	select MSM_JTAG_MM if CORESIGHT_ETM

drivers/pci/controller/pci-msm.c

+5 −13
Original line number Diff line number Diff line
@@ -958,17 +958,6 @@ static void msm_pcie_check_l1ss_support_all(struct msm_pcie_dev_t *dev); 


static void msm_pcie_config_link_pm(struct msm_pcie_dev_t *dev, bool enable);



#ifdef CONFIG_ARM

static void msm_pcie_fixup_irqs(struct msm_pcie_dev_t *dev)

{

	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);

}

#else

static void msm_pcie_fixup_irqs(struct msm_pcie_dev_t *dev)

{

}

#endif



static void msm_pcie_write_reg(void __iomem *base, u32 offset, u32 value)

{

	writel_relaxed(value, base + offset);
@@ -4257,7 +4246,6 @@ int msm_pcie_enumerate(u32 rc_idx) 


	bus = bridge->bus;



	msm_pcie_fixup_irqs(dev);

	pci_assign_unassigned_bus_resources(bus);

	pci_bus_add_devices(bus);
@@ -6640,7 +6628,11 @@ static int msm_pcie_drv_resume(struct msm_pcie_dev_t *pcie_dev) 


	msm_pcie_vreg_init(pcie_dev);



	regulator_enable(pcie_dev->gdsc);

	ret = regulator_enable(pcie_dev->gdsc);

	if (ret)

		PCIE_ERR(pcie_dev,

			"PCIe: RC%d: failed to enable GDSC: ret %d\n",

			pcie_dev->rc_idx, ret);



	if (pcie_dev->icc_path) {

		ret = icc_set_bw(pcie_dev->icc_path, ICC_AVG_BW, ICC_PEAK_BW);