Commit 637d122b authored May 25, 2016 by Marc Zyngier Committed by Christoffer Dall May 31, 2016

KVM: arm/arm64: vgic-v3: Always resample level interrupts



When reading back from the list registers, we need to perform
two actions for level interrupts:
1) clear the soft-pending bit if the interrupt is not pending
   anymore *in the list register*
2) resample the line level and propagate it to the pending state

But these two actions shouldn't be linked, and we should *always*
resample the line level, no matter what state is in the list
register. Otherwise, we may end-up injecting spurious interrupts
that have been already retired.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>

parent df7942d1

virt/kvm/arm/vgic/vgic-v3.c

+9 −5

Original line number	Diff line number	Diff line
		@@ -101,11 +101,15 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
		}
		}

		/* Clear soft pending state when level irqs have been acked */
		if (irq->config == VGIC_CONFIG_LEVEL &&
		!(val & ICH_LR_PENDING_BIT)) {
		/*
		* Clear soft pending state when level irqs have been acked.
		* Always regenerate the pending state.
		*/
		if (irq->config == VGIC_CONFIG_LEVEL) {
		if (!(val & ICH_LR_PENDING_BIT))
		irq->soft_pending = false;
		irq->pending = irq->line_level;

		irq->pending = irq->line_level \|\| irq->soft_pending;
		}

		spin_unlock(&irq->irq_lock);