Loading qcom/lahaina.dtsi +4 −1 Original line number Diff line number Diff line Loading @@ -1412,6 +1412,7 @@ "ref_aux_clk"; clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>; resets = <&ufshc_mem 0>; status = "disabled"; }; Loading @@ -1421,10 +1422,12 @@ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufsphy_mem>; phy-names = "ufsphy"; #reset-cells = <1>; lanes-per-direction = <2>; limit-rate = <1>; /* HS Rate-A */ dev-ref-clk-freq = <0>; /* 19.2 MHz */ qcom,disable-lpm; clock-names = "core_clk", "bus_aggr_clk", Loading Loading
qcom/lahaina.dtsi +4 −1 Original line number Diff line number Diff line Loading @@ -1412,6 +1412,7 @@ "ref_aux_clk"; clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>; resets = <&ufshc_mem 0>; status = "disabled"; }; Loading @@ -1421,10 +1422,12 @@ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufsphy_mem>; phy-names = "ufsphy"; #reset-cells = <1>; lanes-per-direction = <2>; limit-rate = <1>; /* HS Rate-A */ dev-ref-clk-freq = <0>; /* 19.2 MHz */ qcom,disable-lpm; clock-names = "core_clk", "bus_aggr_clk", Loading