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Commit 62ae3115 authored by Deepak Kumar's avatar Deepak Kumar Committed by Gerrit - the friendly Code Review server
Browse files

ARM: dts: msm: Add new GPU DCVS corners for Shima 

GPU clock plan is updated to add new corners SVS_L0 and
LOW_SVS_L1. This change updates the clock plan to add
these new corners.

Change-Id: Ic4fb5fddb838432a3e7b1418c72fd672783fe83a
parent 2a1406de

qcom/shima-gpu.dtsi

+79 −9
Original line number Diff line number Diff line
@@ -143,7 +143,7 @@ 
				#size-cells = <0>;



				qcom,speed-bin = <0>;

				qcom,initial-pwrlevel = <5>;

				qcom,initial-pwrlevel = <7>;



				qcom,gpu-pwrlevel@0 {

					reg = <0>;
@@ -203,6 +203,20 @@ 


				qcom,gpu-pwrlevel@4 {

					reg = <4>;

					qcom,gpu-freq = <490000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;



					qcom,bus-freq-ddr7 = <8>;

					qcom,bus-min-ddr7 = <6>;

					qcom,bus-max-ddr7 = <11>;



					qcom,bus-freq-ddr8 = <7>;

					qcom,bus-min-ddr8 = <6>;

					qcom,bus-max-ddr8 = <10>;

				};



				qcom,gpu-pwrlevel@5 {

					reg = <5>;

					qcom,gpu-freq = <443000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@@ -215,8 +229,22 @@ 
					qcom,bus-max-ddr8 = <9>;

				};



				qcom,gpu-pwrlevel@5 {

					reg = <5>;

				qcom,gpu-pwrlevel@6 {

					reg = <6>;

					qcom,gpu-freq = <365000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;



					qcom,bus-freq-ddr7 = <6>;

					qcom,bus-min-ddr7 = <5>;

					qcom,bus-max-ddr7 = <10>;



					qcom,bus-freq-ddr8 = <6>;

					qcom,bus-min-ddr8 = <5>;

					qcom,bus-max-ddr8 = <9>;

				};



				qcom,gpu-pwrlevel@7 {

					reg = <7>;

					qcom,gpu-freq = <285000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@@ -235,12 +263,12 @@ 
				#size-cells = <0>;



				qcom,speed-bin = <105>;

				qcom,initial-pwrlevel = <2>;

				qcom,initial-pwrlevel = <3>;



				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <490000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;



					qcom,bus-freq-ddr7 = <11>;

					qcom,bus-min-ddr7 = <10>;
@@ -267,6 +295,20 @@ 


				qcom,gpu-pwrlevel@2 {

					reg = <2>;

					qcom,gpu-freq = <365000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;



					qcom,bus-freq-ddr7 = <6>;

					qcom,bus-min-ddr7 = <5>;

					qcom,bus-max-ddr7 = <10>;



					qcom,bus-freq-ddr8 = <6>;

					qcom,bus-min-ddr8 = <5>;

					qcom,bus-max-ddr8 = <9>;

				};



				qcom,gpu-pwrlevel@3 {

					reg = <3>;

					qcom,gpu-freq = <285000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@@ -290,7 +332,7 @@ 
				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <365000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;

					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;



					qcom,bus-freq-ddr7 = <10>;

					qcom,bus-min-ddr7 = <8>;
@@ -321,7 +363,7 @@ 
				#size-cells = <0>;



				qcom,speed-bin = <158>;

				qcom,initial-pwrlevel = <5>;

				qcom,initial-pwrlevel = <7>;



				qcom,gpu-pwrlevel@0 {

					reg = <0>;
@@ -381,6 +423,20 @@ 


				qcom,gpu-pwrlevel@4 {

					reg = <4>;

					qcom,gpu-freq = <490000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;



					qcom,bus-freq-ddr7 = <8>;

					qcom,bus-min-ddr7 = <6>;

					qcom,bus-max-ddr7 = <11>;



					qcom,bus-freq-ddr8 = <7>;

					qcom,bus-min-ddr8 = <6>;

					qcom,bus-max-ddr8 = <10>;

				};



				qcom,gpu-pwrlevel@5 {

					reg = <5>;

					qcom,gpu-freq = <443000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@@ -393,8 +449,22 @@ 
					qcom,bus-max-ddr8 = <9>;

				};



				qcom,gpu-pwrlevel@5 {

					reg = <5>;

				qcom,gpu-pwrlevel@6 {

					reg = <6>;

					qcom,gpu-freq = <365000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;



					qcom,bus-freq-ddr7 = <6>;

					qcom,bus-min-ddr7 = <5>;

					qcom,bus-max-ddr7 = <10>;



					qcom,bus-freq-ddr8 = <6>;

					qcom,bus-min-ddr8 = <5>;

					qcom,bus-max-ddr8 = <9>;

				};



				qcom,gpu-pwrlevel@7 {

					reg = <7>;

					qcom,gpu-freq = <285000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;