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Commit 629a442c authored by Boris Brezillon's avatar Boris Brezillon Committed by Miquel Raynal
Browse files

mtd: rawnand: Fill memorg during detection 



If we want to use the generic NAND layer, we need to have the memorg
struct appropriately filled. Patch the detection code to fill this
struct.

Signed-off-by: default avatarBoris Brezillon <bbrezillon@kernel.org>
Reviewed-by: default avatarFrieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
parent 3020e30a

drivers/mtd/nand/raw/denali.c

+5 −0
Original line number Diff line number Diff line
@@ -1096,6 +1096,9 @@ static int denali_multidev_fixup(struct denali_nand_info *denali) 
{

	struct nand_chip *chip = &denali->nand;

	struct mtd_info *mtd = nand_to_mtd(chip);

	struct nand_memory_organization *memorg;



	memorg = nanddev_get_memorg(&chip->base);



	/*

	 * Support for multi device:
@@ -1125,6 +1128,8 @@ static int denali_multidev_fixup(struct denali_nand_info *denali) 
	}



	/* 2 chips in parallel */

	memorg->pagesize <<= 1;

	memorg->oobsize <<= 1;

	mtd->size <<= 1;

	mtd->erasesize <<= 1;

	mtd->writesize <<= 1;

drivers/mtd/nand/raw/diskonchip.c

+4 −0
Original line number Diff line number Diff line
@@ -1028,6 +1028,7 @@ static inline int __init nftl_partscan(struct mtd_info *mtd, struct mtd_partitio 
{

	struct nand_chip *this = mtd_to_nand(mtd);

	struct doc_priv *doc = nand_get_controller_data(this);

	struct nand_memory_organization *memorg;

	int ret = 0;

	u_char *buf;

	struct NFTLMediaHeader *mh;
@@ -1036,6 +1037,8 @@ static inline int __init nftl_partscan(struct mtd_info *mtd, struct mtd_partitio 
	unsigned blocks, maxblocks;

	int offs, numheaders;



	memorg = nanddev_get_memorg(&this->base);



	buf = kmalloc(mtd->writesize, GFP_KERNEL);

	if (!buf) {

		return 0;
@@ -1082,6 +1085,7 @@ static inline int __init nftl_partscan(struct mtd_info *mtd, struct mtd_partitio 
	   implementation of the NAND layer.  */

	if (mh->UnitSizeFactor != 0xff) {

		this->bbt_erase_shift += (0xff - mh->UnitSizeFactor);

		memorg->pages_per_eraseblock <<= (0xff - mh->UnitSizeFactor);

		mtd->erasesize <<= (0xff - mh->UnitSizeFactor);

		pr_info("Setting virtual erase size to %d\n", mtd->erasesize);

		blocks = mtd->size >> this->bbt_erase_shift;

drivers/mtd/nand/raw/ingenic/jz4740_nand.c

+4 −0
Original line number Diff line number Diff line
@@ -313,8 +313,11 @@ static int jz_nand_detect_bank(struct platform_device *pdev, 
	uint32_t ctrl;

	struct nand_chip *chip = &nand->chip;

	struct mtd_info *mtd = nand_to_mtd(chip);

	struct nand_memory_organization *memorg;

	u8 id[2];



	memorg = nanddev_get_memorg(&chip->base);



	/* Request I/O resource. */

	sprintf(res_name, "bank%d", bank);

	ret = jz_nand_ioremap_resource(pdev, res_name,
@@ -352,6 +355,7 @@ static int jz_nand_detect_bank(struct platform_device *pdev, 


		/* Update size of the MTD. */

		chip->numchips++;

		memorg->ntargets++;

		mtd->size += chip->chipsize;

	}

drivers/mtd/nand/raw/nand_amd.c

+8 −3
Original line number Diff line number Diff line
@@ -20,6 +20,9 @@ 
static void amd_nand_decode_id(struct nand_chip *chip)

{

	struct mtd_info *mtd = nand_to_mtd(chip);

	struct nand_memory_organization *memorg;



	memorg = nanddev_get_memorg(&chip->base);



	nand_decode_ext_id(chip);
@@ -31,9 +34,11 @@ static void amd_nand_decode_id(struct nand_chip *chip) 
	 */

	if (chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 &&

	    chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 &&

	    mtd->writesize == 512) {

		mtd->erasesize = 128 * 1024;

		mtd->erasesize <<= ((chip->id.data[3] & 0x03) << 1);

	    memorg->pagesize == 512) {

		memorg->pages_per_eraseblock = 256;

		memorg->pages_per_eraseblock <<= ((chip->id.data[3] & 0x03) << 1);

		mtd->erasesize = memorg->pages_per_eraseblock *

				 memorg->pagesize;

	}

}

drivers/mtd/nand/raw/nand_base.c

+58 −6
Original line number Diff line number Diff line
@@ -4485,21 +4485,30 @@ static int nand_get_bits_per_cell(u8 cellinfo) 
 */

void nand_decode_ext_id(struct nand_chip *chip)

{

	struct nand_memory_organization *memorg;

	struct mtd_info *mtd = nand_to_mtd(chip);

	int extid;

	u8 *id_data = chip->id.data;



	memorg = nanddev_get_memorg(&chip->base);



	/* The 3rd id byte holds MLC / multichip data */

	memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);

	chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);

	/* The 4th id byte is the important one */

	extid = id_data[3];



	/* Calc pagesize */

	mtd->writesize = 1024 << (extid & 0x03);

	memorg->pagesize = 1024 << (extid & 0x03);

	mtd->writesize = memorg->pagesize;

	extid >>= 2;

	/* Calc oobsize */

	mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);

	memorg->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);

	mtd->oobsize = memorg->oobsize;

	extid >>= 2;

	/* Calc blocksize. Blocksize is multiples of 64KiB */

	memorg->pages_per_eraseblock = ((64 * 1024) << (extid & 0x03)) /

				       memorg->pagesize;

	mtd->erasesize = (64 * 1024) << (extid & 0x03);

	extid >>= 2;

	/* Get buswidth information */
@@ -4516,12 +4525,19 @@ EXPORT_SYMBOL_GPL(nand_decode_ext_id); 
static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)

{

	struct mtd_info *mtd = nand_to_mtd(chip);

	struct nand_memory_organization *memorg;



	memorg = nanddev_get_memorg(&chip->base);



	memorg->pages_per_eraseblock = type->erasesize / type->pagesize;

	mtd->erasesize = type->erasesize;

	mtd->writesize = type->pagesize;

	mtd->oobsize = mtd->writesize / 32;

	memorg->pagesize = type->pagesize;

	mtd->writesize = memorg->pagesize;

	memorg->oobsize = memorg->pagesize / 32;

	mtd->oobsize = memorg->oobsize;



	/* All legacy ID NAND are small-page, SLC */

	memorg->bits_per_cell = 1;

	chip->bits_per_cell = 1;

}
@@ -4550,15 +4566,27 @@ static bool find_full_id_nand(struct nand_chip *chip, 
			      struct nand_flash_dev *type)

{

	struct mtd_info *mtd = nand_to_mtd(chip);

	struct nand_memory_organization *memorg;

	u8 *id_data = chip->id.data;



	memorg = nanddev_get_memorg(&chip->base);



	if (!strncmp(type->id, id_data, type->id_len)) {

		mtd->writesize = type->pagesize;

		memorg->pagesize = type->pagesize;

		mtd->writesize = memorg->pagesize;

		memorg->pages_per_eraseblock = type->erasesize /

					       type->pagesize;

		mtd->erasesize = type->erasesize;

		mtd->oobsize = type->oobsize;

		memorg->oobsize = type->oobsize;

		mtd->oobsize = memorg->oobsize;



		memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);

		chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);

		chip->chipsize = (uint64_t)type->chipsize << 20;

		memorg->eraseblocks_per_lun =

			DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,

					   memorg->pagesize *

					   memorg->pages_per_eraseblock);

		chip->options |= type->options;

		chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);

		chip->ecc_step_ds = NAND_ECC_STEP(type);
@@ -4587,7 +4615,12 @@ static void nand_manufacturer_detect(struct nand_chip *chip) 
	 */

	if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&

	    chip->manufacturer.desc->ops->detect) {

		struct nand_memory_organization *memorg;



		memorg = nanddev_get_memorg(&chip->base);



		/* The 3rd id byte holds MLC / multichip data */

		memorg->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);

		chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);

		chip->manufacturer.desc->ops->detect(chip);

	} else {
@@ -4637,10 +4670,20 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) 
{

	const struct nand_manufacturer *manufacturer;

	struct mtd_info *mtd = nand_to_mtd(chip);

	struct nand_memory_organization *memorg;

	int busw, ret;

	u8 *id_data = chip->id.data;

	u8 maf_id, dev_id;



	/*

	 * Let's start by initializing memorg fields that might be left

	 * unassigned by the ID-based detection logic.

	 */

	memorg = nanddev_get_memorg(&chip->base);

	memorg->planes_per_lun = 1;

	memorg->luns_per_target = 1;

	memorg->ntargets = 1;



	/*

	 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)

	 * after power-up.
@@ -4745,6 +4788,11 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) 
	/* Get chip options */

	chip->options |= type->options;



	memorg->eraseblocks_per_lun =

			DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,

					   memorg->pagesize *

					   memorg->pages_per_eraseblock);



ident_done:

	if (!mtd->name)

		mtd->name = chip->parameters.model;
@@ -4971,10 +5019,13 @@ static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips, 
			   struct nand_flash_dev *table)

{

	struct mtd_info *mtd = nand_to_mtd(chip);

	struct nand_memory_organization *memorg;

	int nand_maf_id, nand_dev_id;

	unsigned int i;

	int ret;



	memorg = nanddev_get_memorg(&chip->base);



	/* Assume all dies are deselected when we enter nand_scan_ident(). */

	chip->cur_cs = -1;
@@ -5042,6 +5093,7 @@ static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips, 
		pr_info("%d chips detected\n", i);



	/* Store the number of chips and calc total size for mtd */

	memorg->ntargets = i;

	chip->numchips = i;

	mtd->size = i * chip->chipsize;