Merge 71b985ba on remote branch

	* cti-flush-trig-num: Specifies the flush CTI trigger number for TMC

	  ETR and TMC ETF.

	* qcom,qdss-ipa-support : indicates whether qdss to ipa bam connection

	   need to support.

* Optional property for CATU and APSS :

	* interrupts : Exactly one SPI may be listed for reporting the address

	  error for CATU and four interrupts for TGU to get trigger from four

			should have the "pdmem-domainX" to indicate the

			corresponding bases.

- qcom,sdpm-cx-mx-<id>

	Usage:		Optional

	Value type:	<prop-encoded-array>

	Definition:	Addresses and sizes for the SDPM memory of the HW bases

			in each frequency domain, indicated by an "id"(0/1/2).

* Property qcom,freq-domain

Devices supporting freq-domain must set their "qcom,freq-domain" property with

phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.

		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

		clock-names = "xo", "alternate";

		qcom,sdpm-cx-mx-1 = <0x00636f08 0x4>;

		qcom,sdpm-cx-mx-2 = <0x00636f0c 0x4>;

		#freq-domain-cells = <1>;

	};

- qcom,chipid:		   If it exists this property is used to replace

			   the chip identification read from the GPU hardware.

			   This is used to override faulty hardware readings.

- qcom,gpu-model:	   If it exists this property is used for GPU model name.

- qcom,disable-wake-on-touch:   Boolean. Disables the GPU power up on a touch input event.

- qcom,disable-busy-time-burst:

				Boolean. Disables the busy time burst to avoid switching

				the threshold set by KGSL_GOVERNOR_CALL_INTERVAL. Enable only if

				target has NAP state enabled.

 nvmem-cells:

				A phandle to the configuration data such as gpu speed bin, gpu gaming mode

				provided by a nvmem device. If unspecified default values shall be used.

				A phandle to the configuration data such as gpu speed bin, gpu gaming mode,

				gpu model name provided by a nvmem device. If unspecified default values shall be used.

 nvmem-cell-names:

				Should be "speed_bin", "gaming_bin"

				Should be "speed_bin", "gaming_bin", "gpu_model"

GPU Quirks:

- qcom,gpu-quirk-two-pass-use-wfi:

- qcom,mempool-reserved:	Number of pages reserved at init time for a pool.

- qcom,mempool-allocate:	Allocate memory from the system memory when the

				reserved pool exhausted.

GPU model configuration:

- qcom,gpu-models:

		Container of sets of GPU model names specified by qcom,gpu-models.

Properties:

- compatible:

		Must be qcom,gpu-models.

- qcom,gpu-model:

		Defines a GPU model name for specific GPU model ID.

Properties:

-  qcom,gpu-model-id:

		Identifier for the specific GPU hardware configuration  - must match the value read

		from the hardware.

- qcom,gpu-model:

		GPU model name for a specific GPU hardware.

SOC Hardware revisions:

- qcom,soc-hw-revisions:

		vdd-parent-supply = <&VDD_GFX_LEVEL>;

		vdd-parent-min-corner = <RPM_SMD_REGULATOR_LEVEL_RETENTION>;

		nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;

		nvmem-cell-names = "speed_bin", "gaming_bin";

		nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>, <&gpu_model_bin>;

		nvmem-cell-names = "speed_bin", "gaming_bin","gpu_model";

		/* IOMMU Data */

		iommu = <&gfx_iommu>;

			};

		};

		qcom,gpu-models {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible="qcom,gpu-models";

			qcom,gpu-model@0 {

				qcom,gpu-model-id = <0>;

				qcom,gpu-model = "Adreno642Lv1";

			};

		}

		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells= <1>;

Qualcomm Technologies, Inc. Direwolf Network-On-Chip interconnect driver binding

------------------------------------------------------------------------------

Direwolf interconnect providers support system bandwidth requirements through

RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is

able to communicate with the BCM through the Resource State Coordinator (RSC)

associated with each execution environment. Provider nodes must point to at

least one RPMh device child node pertaining to their RSC and each provider

can map to multiple RPMh resources.

Required properties :

- compatible : shall contain only one of the following:

		"qcom,direwolf-aggre1_noc";

		"qcom,direwolf-aggre2_noc";

		"qcom,direwolf-clk_virt";

		"qcom,direwolf-config_noc";

		"qcom,direwolf-dc_noc";

		"qcom,direwolf-gem_noc";

		"qcom,direwolf-lpass_ag_noc";

		"qcom,direwolf-mc_virt";

		"qcom,direwolf-mmss_noc";

		"qcom,direwolf-nspa_noc";

		"qcom,direwolf-nspb_noc";

		"qcom,direwolf-system_noc_main";

- #interconnect-cells : should contain 1

Examples:

aggre1_noc: interconnect@16c0000 {

	"qcom,direwolf-aggre1_noc";

	interconnect-cells = <1>;

};

	Usage:      optional

	Value type: <u32>

	Definition:  Controls the order of powering up BOOST, LDO AND NCP

		     blocks. Appilcable for PM7325B. Possible values are: 0, 1, 2, 3, 4.

		     blocks. Applicable for PM7325B. Possible values are: 0, 1, 2, 3, 4.

		     0 - Boost, LDO, NCP

		     1 - Boost, LDO

		     2 - Boost, NCP

		     3 - Boost only

		     4 - Boost, NCP, LDO

- qcom,high-p2-blank-time-ns

	Usage:      optional

	Value type: <u32>

	Definition:  Controls the higher clamp threshold for p2 minimum on time.

		     Applicable for PM7325B. Possible values are 40, 69, 99, 129, 159,

		     189, 220, 250.

- qcom,low-p2-blank-time-ns

	Usage:      optional

	Value type: <u32>

	Definition:  Controls the lower clamp threshold for p2 minimum on time.

		     Applicable for PM7325B. Possible values are 40, 69, 99, 129, 159,

		     189, 220, 250.

- qcom,mpc-current-thr-ma

	Usage:      optional

	Value type: <u32>

	Definition:  Controls the mpc threshold for inductor current after start up

		     is done. Applicable for PM7325B. Possible values are 160, 200, 240,

		     280, 320, 360, 400, 440.

Touch-to-wake (TTW) properties:

TTW supports 2 modes of operation - HW and SW. In the HW mode the enable/disable