Merge "clk: qcom: clk-rcg2: Fix possible dereference of clk parent for dfs clocks" (623d5c82) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/clk/qcom/clk-debug.c

+5 −1

Original line number	Diff line number	Diff line
		@@ -146,13 +146,17 @@ static u8 clk_debug_mux_get_parent(struct clk_hw *hw)
		{
		int i, num_parents = clk_hw_get_num_parents(hw);
		struct clk_hw *hw_clk = clk_hw_get_parent(hw);
		struct clk_hw *clk_parent;
		const char *parent;

		if (!hw_clk)
		return 0;

		for (i = 0; i < num_parents; i++) {
		parent = clk_hw_get_name(clk_hw_get_parent_by_index(hw, i));
		clk_parent = clk_hw_get_parent_by_index(hw, i);
		if (!clk_parent)
		return 0;
		parent = clk_hw_get_name(clk_parent);
		if (!strcmp(parent, clk_hw_get_name(hw_clk))) {
		pr_debug("%s: clock parent - %s, index %d\n", __func__,
		parent, i);

drivers/clk/qcom/clk-rcg2.c

+12 −6

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved.
		* Copyright (c) 2013, 2016-2020, The Linux Foundation. All rights reserved.
		*/

		#include <linux/kernel.h>
		@@ -1435,7 +1435,7 @@ const struct clk_ops clk_rcg2_shared_ops = {
		EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);

		/* Common APIs to be used for DFS based RCGR */
		static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
		static int clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
		struct freq_tbl *f)
		{
		struct clk_rcg2 *rcg = to_clk_rcg2(hw);
		@@ -1462,6 +1462,8 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
		if (src == rcg->parent_map[i].cfg) {
		f->src = rcg->parent_map[i].src;
		p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);
		if (!p)
		return -EINVAL;
		prate = clk_hw_get_rate(p);
		}
		}
		@@ -1482,12 +1484,13 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
		}

		f->freq = calc_rate(prate, f->m, f->n, mode, f->pre_div);
		return 0;
		}

		static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg)
		{
		struct freq_tbl *freq_tbl;
		int i;
		int i, ret;

		/* Allocate space for 1 extra since table is NULL terminated */
		freq_tbl = kcalloc(MAX_PERF_LEVEL + 1, sizeof(*freq_tbl), GFP_KERNEL);
		@@ -1495,10 +1498,13 @@ static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg)
		return -ENOMEM;
		rcg->freq_tbl = freq_tbl;

		for (i = 0; i < MAX_PERF_LEVEL; i++)
		for (i = 0; i < MAX_PERF_LEVEL; i++) {
		ret =
		clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i);

		return 0;
		if (ret)
		return ret;
		}
		return ret;
		}

		static int clk_rcg2_dfs_determine_rate(struct clk_hw *hw,

drivers/clk/qcom/gdsc-regulator.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -374,10 +374,12 @@ static int gdsc_disable(struct regulator_dev *rdev)
		udelay(TIMEOUT_US);
		} else {
		ret = poll_gdsc_status(sc, DISABLED);
		if (ret)
		if (ret) {
		regmap_read(sc->regmap, REG_OFFSET, &regval);
		dev_err(&rdev->dev, "%s disable timed out: 0x%x\n",
		sc->rdesc.name, regval);
		}
		}

		if (sc->domain_addr) {
		regmap_read(sc->domain_addr, REG_OFFSET, &regval);