Loading msm/sde/sde_hw_catalog.c +8 −0 Original line number Diff line number Diff line Loading @@ -161,6 +161,7 @@ enum sde_prop { SDE_OFF, SDE_LEN, SSPP_LINEWIDTH, VIG_SSPP_LINEWIDTH, MIXER_LINEWIDTH, MIXER_BLEND, WB_LINEWIDTH, Loading Loading @@ -450,6 +451,7 @@ static struct sde_prop_type sde_prop[] = { {SDE_OFF, "qcom,sde-off", true, PROP_TYPE_U32}, {SDE_LEN, "qcom,sde-len", false, PROP_TYPE_U32}, {SSPP_LINEWIDTH, "qcom,sde-sspp-linewidth", false, PROP_TYPE_U32}, {VIG_SSPP_LINEWIDTH, "qcom,sde-vig-sspp-linewidth", false, PROP_TYPE_U32}, {MIXER_LINEWIDTH, "qcom,sde-mixer-linewidth", false, PROP_TYPE_U32}, {MIXER_BLEND, "qcom,sde-mixer-blendstages", false, PROP_TYPE_U32}, {WB_LINEWIDTH, "qcom,sde-wb-linewidth", false, PROP_TYPE_U32}, Loading Loading @@ -1037,6 +1039,7 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk, bool *prop_exists, struct sde_prop_value *prop_value, u32 *vig_count) { sblk->maxlinewidth = sde_cfg->vig_sspp_linewidth; sblk->maxupscale = MAX_UPSCALE_RATIO; sblk->maxdwnscale = MAX_DOWNSCALE_RATIO; sspp->id = SSPP_VIG0 + *vig_count; Loading Loading @@ -3057,6 +3060,11 @@ static int _sde_parse_prop_check(struct sde_mdss_cfg *cfg, if (!prop_exists[SSPP_LINEWIDTH]) cfg->max_sspp_linewidth = DEFAULT_SDE_LINE_WIDTH; cfg->vig_sspp_linewidth = PROP_VALUE_ACCESS(prop_value, VIG_SSPP_LINEWIDTH, 0); if (!prop_exists[VIG_SSPP_LINEWIDTH]) cfg->vig_sspp_linewidth = cfg->max_sspp_linewidth; cfg->max_mixer_width = PROP_VALUE_ACCESS(prop_value, MIXER_LINEWIDTH, 0); if (!prop_exists[MIXER_LINEWIDTH]) Loading msm/sde/sde_hw_catalog.h +2 −0 Original line number Diff line number Diff line Loading @@ -1185,6 +1185,7 @@ struct sde_perf_cfg { * register offsets, capabilities of the all MDSS HW sub-blocks. * * @max_sspp_linewidth max source pipe line width support. * @vig_sspp_linewidth max vig source pipe line width support. * @max_mixer_width max layer mixer line width support. * @max_mixer_blendstages max layer mixer blend stages or * supported z order Loading Loading @@ -1251,6 +1252,7 @@ struct sde_mdss_cfg { u32 hwversion; u32 max_sspp_linewidth; u32 vig_sspp_linewidth; u32 max_mixer_width; u32 max_mixer_blendstages; u32 max_wb_linewidth; Loading Loading
msm/sde/sde_hw_catalog.c +8 −0 Original line number Diff line number Diff line Loading @@ -161,6 +161,7 @@ enum sde_prop { SDE_OFF, SDE_LEN, SSPP_LINEWIDTH, VIG_SSPP_LINEWIDTH, MIXER_LINEWIDTH, MIXER_BLEND, WB_LINEWIDTH, Loading Loading @@ -450,6 +451,7 @@ static struct sde_prop_type sde_prop[] = { {SDE_OFF, "qcom,sde-off", true, PROP_TYPE_U32}, {SDE_LEN, "qcom,sde-len", false, PROP_TYPE_U32}, {SSPP_LINEWIDTH, "qcom,sde-sspp-linewidth", false, PROP_TYPE_U32}, {VIG_SSPP_LINEWIDTH, "qcom,sde-vig-sspp-linewidth", false, PROP_TYPE_U32}, {MIXER_LINEWIDTH, "qcom,sde-mixer-linewidth", false, PROP_TYPE_U32}, {MIXER_BLEND, "qcom,sde-mixer-blendstages", false, PROP_TYPE_U32}, {WB_LINEWIDTH, "qcom,sde-wb-linewidth", false, PROP_TYPE_U32}, Loading Loading @@ -1037,6 +1039,7 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk, bool *prop_exists, struct sde_prop_value *prop_value, u32 *vig_count) { sblk->maxlinewidth = sde_cfg->vig_sspp_linewidth; sblk->maxupscale = MAX_UPSCALE_RATIO; sblk->maxdwnscale = MAX_DOWNSCALE_RATIO; sspp->id = SSPP_VIG0 + *vig_count; Loading Loading @@ -3057,6 +3060,11 @@ static int _sde_parse_prop_check(struct sde_mdss_cfg *cfg, if (!prop_exists[SSPP_LINEWIDTH]) cfg->max_sspp_linewidth = DEFAULT_SDE_LINE_WIDTH; cfg->vig_sspp_linewidth = PROP_VALUE_ACCESS(prop_value, VIG_SSPP_LINEWIDTH, 0); if (!prop_exists[VIG_SSPP_LINEWIDTH]) cfg->vig_sspp_linewidth = cfg->max_sspp_linewidth; cfg->max_mixer_width = PROP_VALUE_ACCESS(prop_value, MIXER_LINEWIDTH, 0); if (!prop_exists[MIXER_LINEWIDTH]) Loading
msm/sde/sde_hw_catalog.h +2 −0 Original line number Diff line number Diff line Loading @@ -1185,6 +1185,7 @@ struct sde_perf_cfg { * register offsets, capabilities of the all MDSS HW sub-blocks. * * @max_sspp_linewidth max source pipe line width support. * @vig_sspp_linewidth max vig source pipe line width support. * @max_mixer_width max layer mixer line width support. * @max_mixer_blendstages max layer mixer blend stages or * supported z order Loading Loading @@ -1251,6 +1252,7 @@ struct sde_mdss_cfg { u32 hwversion; u32 max_sspp_linewidth; u32 vig_sspp_linewidth; u32 max_mixer_width; u32 max_mixer_blendstages; u32 max_wb_linewidth; Loading