Commit 61d3edb8 authored Mar 27, 2014 by Manuel Lauss Committed by Ralf Baechle Mar 31, 2014

MIPS: Alchemy: remove duplicate UART register offset definitions



The UART register names are identical to the ones in uapi/linux/serial_reg.h,
which causes build failures in various drivers when they indirectly pull in
the au1000.h header, for example via gpio.h:

In file included from arch/mips/include/asm/mach-au1x00/gpio.h:13:0,
                 from arch/mips/include/asm/gpio.h:4,
                 from include/linux/gpio.h:48,
                 from include/linux/ssb/ssb.h:9,
                 from drivers/ssb/driver_mipscore.c:11:
arch/mips/include/asm/mach-au1x00/au1000.h:1171:0: note: this is the location of the previous definition
 #define UART_LSR 0x1C /* Line Status Register */

Get rid of the altogether, nothing in the core Alchemy code depends
on them any more.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/6664/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent e6086557

arch/mips/include/asm/mach-au1x00/au1000.h

+0 −12

Original line number	Diff line number	Diff line
		@@ -1161,18 +1161,6 @@ enum soc_au1200_ints {
		#define MAC_RX_BUFF3_STATUS 0x30
		#define MAC_RX_BUFF3_ADDR 0x34

		#define UART_RX 0 /* Receive buffer */
		#define UART_TX 4 /* Transmit buffer */
		#define UART_IER 8 /* Interrupt Enable Register */
		#define UART_IIR 0xC /* Interrupt ID Register */
		#define UART_FCR 0x10 /* FIFO Control Register */
		#define UART_LCR 0x14 /* Line Control Register */
		#define UART_MCR 0x18 /* Modem Control Register */
		#define UART_LSR 0x1C /* Line Status Register */
		#define UART_MSR 0x20 /* Modem Status Register */
		#define UART_CLK 0x28 /* Baud Rate Clock Divider */
		#define UART_MOD_CNTRL 0x100 /* Module Control */

		/* SSIO */
		#define SSI0_STATUS 0xB1600000
		# define SSI_STATUS_BF (1 << 4)