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Commit 61aee934 authored by YH Huang's avatar YH Huang Committed by Matthias Brugger
Browse files

arm64: dts: mt8173: add MT8173 display PWM driver support node 



Add display PWM node in mt8173-evb.dts and mt8173.dtsi.

Signed-off-by: default avatarYH Huang <yh.huang@mediatek.com>
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent b2c76e27

arch/arm64/boot/dts/mediatek/mt8173-evb.dts

+13 −0
Original line number Diff line number Diff line
@@ -92,6 +92,13 @@ 
};



&pio {

	disp_pwm0_pins: disp_pwm0_pins {

		pins1 {

			pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;

			output-low;

		};

	};



	mmc0_pins_default: mmc0default {

		pins_cmd_dat {

			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
@@ -190,6 +197,12 @@ 
	};

};



&pwm0 {

	pinctrl-names = "default";

	pinctrl-0 = <&disp_pwm0_pins>;

	status = "okay";

};



&pwrap {

	pmic: mt6397 {

		compatible = "mediatek,mt6397";

arch/arm64/boot/dts/mediatek/mt8173.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -525,6 +525,28 @@ 
			#clock-cells = <1>;

		};



		pwm0: pwm@1401e000 {

			compatible = "mediatek,mt8173-disp-pwm",

				     "mediatek,mt6595-disp-pwm";

			reg = <0 0x1401e000 0 0x1000>;

			#pwm-cells = <2>;

			clocks = <&mmsys CLK_MM_DISP_PWM026M>,

				 <&mmsys CLK_MM_DISP_PWM0MM>;

			clock-names = "main", "mm";

			status = "disabled";

		};



		pwm1: pwm@1401f000 {

			compatible = "mediatek,mt8173-disp-pwm",

				     "mediatek,mt6595-disp-pwm";

			reg = <0 0x1401f000 0 0x1000>;

			#pwm-cells = <2>;

			clocks = <&mmsys CLK_MM_DISP_PWM126M>,

				 <&mmsys CLK_MM_DISP_PWM1MM>;

			clock-names = "main", "mm";

			status = "disabled";

		};



		imgsys: clock-controller@15000000 {

			compatible = "mediatek,mt8173-imgsys", "syscon";

			reg = <0 0x15000000 0 0x1000>;