Commit 618cf883 authored Mar 07, 2019 by José Roberto de Souza

drm/i915: Disable PSR2 while getting pipe CRC



When PSR2 is active aka after the number of frames programmed in
PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC
interrupts causing IGT tests to fail due timeout.

This same behavior don't happen with PSR1, as soon as pipe CRC is
enabled it blocks PSR1 activation so CRC calculation continues to
happens normaly.

This patch also set mode_changed as true when PSR is available to
force atomic check functions to compute new PSR state, otherwise PSR2
would not be disabled.

v4: Only setting mode_changed if has_psr is set(Dhinakaran)

v3: Reusing intel_crtc_crc_prepare() and crc_enabled, only setting
mode_changed if it can do PSR.

v2: Changed commit description to describe that PSR2 inhibit CRC
calculations.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190308000050.6226-6-jose.souza@intel.com

parent a8ebf607

drivers/gpu/drm/i915/intel_pipe_crc.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -306,6 +306,7 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
		goto put_state;
		}

		pipe_config->base.mode_changed = pipe_config->has_psr;
		pipe_config->crc_enabled = enable;

		if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A) {

drivers/gpu/drm/i915/intel_psr.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -572,6 +572,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
		return false;
		}

		if (crtc_state->crc_enabled) {
		DRM_DEBUG_KMS("PSR2 not enabled because it would inhibit pipe CRC calculation\n");
		return false;
		}

		return true;
		}