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Commit 615f8fd9 authored by Eliezer Tamir's avatar Eliezer Tamir Committed by David S. Miller
Browse files

[BNX2X]: fix MSI-X/INT#A errata 



Errata A0.158 workaround. 

Running in INT#A mode after running with MSI-X fails due to a PCI core
bug.

Signed-off-by: default avatarEliezer Tamir <eliezert@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 0e39e645

drivers/net/bnx2x.c

+16 −8
Original line number Original line Diff line number Diff line
@@ -443,7 +443,7 @@ static void bnx2x_panic_dump(struct bnx2x *bp) 
	DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n");

	DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n");

}

}





static void bnx2x_enable_int(struct bnx2x *bp)

static void bnx2x_int_enable(struct bnx2x *bp)

{

{

	int port = bp->port;

	int port = bp->port;

	u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;

	u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
@@ -456,18 +456,26 @@ static void bnx2x_enable_int(struct bnx2x *bp) 
			HC_CONFIG_0_REG_ATTN_BIT_EN_0);

			HC_CONFIG_0_REG_ATTN_BIT_EN_0);

	} else {

	} else {

		val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |

		val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |

			HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |

			HC_CONFIG_0_REG_INT_LINE_EN_0 |

			HC_CONFIG_0_REG_INT_LINE_EN_0 |

			HC_CONFIG_0_REG_ATTN_BIT_EN_0);

			HC_CONFIG_0_REG_ATTN_BIT_EN_0);



		/* Errata A0.158 workaround */

		DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  MSI-X %d\n",

		   val, port, addr, msix);



		REG_WR(bp, addr, val);



		val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;

		val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;

	}

	}





	DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  msi %d\n",

	DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  MSI-X %d\n",

	   val, port, addr, msix);

	   val, port, addr, msix);





	REG_WR(bp, addr, val);

	REG_WR(bp, addr, val);

}

}





static void bnx2x_disable_int(struct bnx2x *bp)

static void bnx2x_int_disable(struct bnx2x *bp)

{

{

	int port = bp->port;

	int port = bp->port;

	u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;

	u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
@@ -486,7 +494,7 @@ static void bnx2x_disable_int(struct bnx2x *bp) 
		BNX2X_ERR("BUG! proper val not read from IGU!\n");

		BNX2X_ERR("BUG! proper val not read from IGU!\n");

}

}





static void bnx2x_disable_int_sync(struct bnx2x *bp)

static void bnx2x_int_disable_sync(struct bnx2x *bp)

{

{





	int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;

	int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
@@ -494,7 +502,7 @@ static void bnx2x_disable_int_sync(struct bnx2x *bp) 




	atomic_inc(&bp->intr_sem);

	atomic_inc(&bp->intr_sem);

	/* prevent the HW from sending interrupts */

	/* prevent the HW from sending interrupts */

	bnx2x_disable_int(bp);

	bnx2x_int_disable(bp);





	/* make sure all ISRs are done */

	/* make sure all ISRs are done */

	if (msix) {

	if (msix) {
@@ -5710,7 +5718,7 @@ static void bnx2x_nic_init(struct bnx2x *bp) 
	bnx2x_init_internal(bp);

	bnx2x_init_internal(bp);

	bnx2x_init_stats(bp);

	bnx2x_init_stats(bp);

	bnx2x_init_ind_table(bp);

	bnx2x_init_ind_table(bp);

	bnx2x_enable_int(bp);

	bnx2x_int_enable(bp);





}

}
@@ -7154,7 +7162,7 @@ static int bnx2x_nic_load(struct bnx2x *bp, int req_irq) 
		napi_disable(&bnx2x_fp(bp, i, napi));

		napi_disable(&bnx2x_fp(bp, i, napi));





int_disable:

int_disable:

	bnx2x_disable_int_sync(bp);

	bnx2x_int_disable_sync(bp);





	bnx2x_free_skbs(bp);

	bnx2x_free_skbs(bp);

	bnx2x_free_irq(bp);

	bnx2x_free_irq(bp);
@@ -7174,7 +7182,7 @@ static void bnx2x_netif_stop(struct bnx2x *bp) 
	bp->rx_mode = BNX2X_RX_MODE_NONE;

	bp->rx_mode = BNX2X_RX_MODE_NONE;

	bnx2x_set_storm_rx_mode(bp);

	bnx2x_set_storm_rx_mode(bp);





	bnx2x_disable_int_sync(bp);

	bnx2x_int_disable_sync(bp);

	bnx2x_link_reset(bp);

	bnx2x_link_reset(bp);





	for_each_queue(bp, i)

	for_each_queue(bp, i)