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Commit 615740fd authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge branch 'clockevents/4.21' of... 

Merge branch 'clockevents/4.21' of http://git.linaro.org/people/daniel.lezcano/linux into timers/core

Pull clocksource/event changes from Daniel Lezcano:

 - Add the sched_clock for the arc timer (Alexey Brodkin)

 - Change the file timer names for riscv, rockchip, tegra20, sun4i and
   meson6 (Daniel Lezcano)

 - Add the DT bindings for r8a7796, r8a77470 and r8a774a1 (Biju Das)

 - Remove the early platform driver registration for timer-ti-dm (Bartosz
   Golaszewski)

 - Provide the sched_clock for the riscv timer (Anup Patel)

 - Add support for ARM64 for the imx-gpt and convert the imx-tpm to the
   timer-of API (Anson Huang)

 - Remove useless irq protection for the imx-gpt (Clément Péron)

 - Remove a duplicate function name for the vt8500 (Dan Carpenter)

 - Remove obsolete inclusion of <asm/smp_twd.h> for the tegra20 (Geert
   Uytterhoeven)

 - Demote the prcmu and the custom sched_clock for the dbx500 and the ux500
   (Linus Walleij)

 - Add a new timer clock for the RDA8810PL (Manivannan Sadhasivam)

 - Rename the macro to stick to the register name and add the delay timer
   (Martin Blumenstingl)

 - Switch the bcm2835 to the SPDX identifier (Stefan Wahren)

 - Fix the interrupt register access on the fttmr010 (Tao Ren)

 - Add missing of_node_put in the initialization path on the
   integrator-ap (Yangtao Li)
parents 07daef8b 7f83a132

Documentation/devicetree/bindings/timer/renesas,cmt.txt

+12 −3
Original line number Diff line number Diff line
@@ -28,6 +28,10 @@ Required Properties: 
    - "renesas,r8a7744-cmt1" for the 48-bit CMT1 device included in r8a7744.

    - "renesas,r8a7745-cmt0" for the 32-bit CMT0 device included in r8a7745.

    - "renesas,r8a7745-cmt1" for the 48-bit CMT1 device included in r8a7745.

    - "renesas,r8a77470-cmt0" for the 32-bit CMT0 device included in r8a77470.

    - "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470.

    - "renesas,r8a774a1-cmt0" for the 32-bit CMT0 device included in r8a774a1.

    - "renesas,r8a774a1-cmt1" for the 48-bit CMT1 device included in r8a774a1.

    - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790.

    - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790.

    - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791.
@@ -36,6 +40,8 @@ Required Properties: 
    - "renesas,r8a7793-cmt1" for the 48-bit CMT1 device included in r8a7793.

    - "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794.

    - "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794.

    - "renesas,r8a7796-cmt0" for the 32-bit CMT0 device included in r8a7796.

    - "renesas,r8a7796-cmt1" for the 48-bit CMT1 device included in r8a7796.

    - "renesas,r8a77970-cmt0" for the 32-bit CMT0 device included in r8a77970.

    - "renesas,r8a77970-cmt1" for the 48-bit CMT1 device included in r8a77970.

    - "renesas,r8a77980-cmt0" for the 32-bit CMT0 device included in r8a77980.
@@ -47,9 +53,12 @@ Required Properties: 
		and RZ/G1.

		These are fallbacks for r8a73a4, R-Car Gen2 and RZ/G1 entries

		listed above.

    - "renesas,rcar-gen3-cmt0" for 32-bit CMT0 devices included in R-Car Gen3.

    - "renesas,rcar-gen3-cmt1" for 48-bit CMT1 devices included in R-Car Gen3.

		These are fallbacks for R-Car Gen3 entries listed above.

    - "renesas,rcar-gen3-cmt0" for 32-bit CMT0 devices included in R-Car Gen3

		and RZ/G2.

    - "renesas,rcar-gen3-cmt1" for 48-bit CMT1 devices included in R-Car Gen3

		and RZ/G2.

		These are fallbacks for R-Car Gen3 and RZ/G2 entries listed

		above.



  - reg: base address and length of the registers block for the timer module.

  - interrupts: interrupt-specifier for the timer, one per channel.

arch/arc/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ config ARC 
	select GENERIC_IRQ_SHOW

	select GENERIC_PCI_IOMAP

	select GENERIC_PENDING_IRQ if SMP

	select GENERIC_SCHED_CLOCK

	select GENERIC_SMP_IDLE_THREAD

	select HAVE_ARCH_KGDB

	select HAVE_ARCH_TRACEHOOK

drivers/clocksource/Kconfig

+11 −15
Original line number Diff line number Diff line
@@ -105,6 +105,14 @@ config OWL_TIMER 
	help

	  Enables the support for the Actions Semi Owl timer driver.



config RDA_TIMER

	bool "RDA timer driver" if COMPILE_TEST

	depends on GENERIC_CLOCKEVENTS

	select CLKSRC_MMIO

	select TIMER_OF

	help

	  Enables the support for the RDA Micro timer driver.



config SUN4I_TIMER

	bool "Sun4i timer driver" if COMPILE_TEST

	depends on HAS_IOMEM
@@ -163,12 +171,6 @@ config CLKSRC_NOMADIK_MTU 
	  to multiple interrupt generating programmable

	  32-bit free running decrementing counters.



config CLKSRC_NOMADIK_MTU_SCHED_CLOCK

	bool

	depends on CLKSRC_NOMADIK_MTU

	help

	  Use the Multi Timer Unit as the sched_clock.



config CLKSRC_DBX500_PRCMU

	bool "Clocksource PRCMU Timer" if COMPILE_TEST

	depends on HAS_IOMEM
@@ -226,13 +228,6 @@ config INTEGRATOR_AP_TIMER 
	help

	  Enables support for the Integrator-ap timer.



config CLKSRC_DBX500_PRCMU_SCHED_CLOCK

	bool "Clocksource PRCMU Timer sched_clock"

	depends on (CLKSRC_DBX500_PRCMU && !CLKSRC_NOMADIK_MTU_SCHED_CLOCK)

	default y

	help

	  Use the always on PRCMU Timer as sched_clock



config CLKSRC_EFM32

	bool "Clocksource for Energy Micro's EFM32 SoCs" if !ARCH_EFM32

	depends on OF && ARM && (ARCH_EFM32 || COMPILE_TEST)
@@ -290,6 +285,7 @@ config CLKSRC_MPS2 


config ARC_TIMERS

	bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST

	depends on GENERIC_SCHED_CLOCK

	select TIMER_OF

	help

	  These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
@@ -580,7 +576,7 @@ config H8300_TPU 


config CLKSRC_IMX_GPT

	bool "Clocksource using i.MX GPT" if COMPILE_TEST

	depends on ARM && CLKDEV_LOOKUP

	depends on (ARM || ARM64) && CLKDEV_LOOKUP

	select CLKSRC_MMIO



config CLKSRC_IMX_TPM
@@ -611,7 +607,7 @@ config ATCPIT100_TIMER 


config RISCV_TIMER

	bool "Timer for the RISC-V platform"

	depends on RISCV

	depends on GENERIC_SCHED_CLOCK && RISCV

	default y

	select TIMER_PROBE

	select TIMER_OF

drivers/clocksource/Makefile

+6 −5
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ obj-$(CONFIG_OMAP_DM_TIMER) += timer-ti-dm.o 
obj-$(CONFIG_DW_APB_TIMER)	+= dw_apb_timer.o

obj-$(CONFIG_DW_APB_TIMER_OF)	+= dw_apb_timer_of.o

obj-$(CONFIG_FTTMR010_TIMER)	+= timer-fttmr010.o

obj-$(CONFIG_ROCKCHIP_TIMER)      += rockchip_timer.o

obj-$(CONFIG_ROCKCHIP_TIMER)      += timer-rockchip.o

obj-$(CONFIG_CLKSRC_NOMADIK_MTU)	+= nomadik-mtu.o

obj-$(CONFIG_CLKSRC_DBX500_PRCMU)	+= clksrc-dbx500-prcmu.o

obj-$(CONFIG_ARMADA_370_XP_TIMER)	+= timer-armada-370-xp.o
@@ -32,10 +32,10 @@ obj-$(CONFIG_MXS_TIMER) += mxs_timer.o 
obj-$(CONFIG_CLKSRC_PXA)	+= pxa_timer.o

obj-$(CONFIG_PRIMA2_TIMER)	+= timer-prima2.o

obj-$(CONFIG_U300_TIMER)	+= timer-u300.o

obj-$(CONFIG_SUN4I_TIMER)	+= sun4i_timer.o

obj-$(CONFIG_SUN4I_TIMER)	+= timer-sun4i.o

obj-$(CONFIG_SUN5I_HSTIMER)	+= timer-sun5i.o

obj-$(CONFIG_MESON6_TIMER)	+= meson6_timer.o

obj-$(CONFIG_TEGRA_TIMER)	+= tegra20_timer.o

obj-$(CONFIG_MESON6_TIMER)	+= timer-meson6.o

obj-$(CONFIG_TEGRA_TIMER)	+= timer-tegra20.o

obj-$(CONFIG_VT8500_TIMER)	+= timer-vt8500.o

obj-$(CONFIG_NSPIRE_TIMER)	+= timer-zevio.o

obj-$(CONFIG_BCM_KONA_TIMER)	+= bcm_kona_timer.o
@@ -57,6 +57,7 @@ obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o 
obj-$(CONFIG_OWL_TIMER)		+= timer-owl.o

obj-$(CONFIG_SPRD_TIMER)	+= timer-sprd.o

obj-$(CONFIG_NPCM7XX_TIMER)	+= timer-npcm7xx.o

obj-$(CONFIG_RDA_TIMER)		+= timer-rda.o



obj-$(CONFIG_ARC_TIMERS)		+= arc_timer.o

obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
@@ -78,6 +79,6 @@ obj-$(CONFIG_H8300_TPU) += h8300_tpu.o 
obj-$(CONFIG_CLKSRC_ST_LPC)		+= clksrc_st_lpc.o

obj-$(CONFIG_X86_NUMACHIP)		+= numachip.o

obj-$(CONFIG_ATCPIT100_TIMER)		+= timer-atcpit100.o

obj-$(CONFIG_RISCV_TIMER)		+= riscv_timer.o

obj-$(CONFIG_RISCV_TIMER)		+= timer-riscv.o

obj-$(CONFIG_CSKY_MP_TIMER)		+= timer-mp-csky.o

obj-$(CONFIG_GX6605S_TIMER)		+= timer-gx6605s.o

drivers/clocksource/arc_timer.c

+22 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include <linux/cpu.h>

#include <linux/of.h>

#include <linux/of_irq.h>

#include <linux/sched_clock.h>



#include <soc/arc/timers.h>

#include <soc/arc/mcip.h>
@@ -88,6 +89,11 @@ static u64 arc_read_gfrc(struct clocksource *cs) 
	return (((u64)h) << 32) | l;

}



static notrace u64 arc_gfrc_clock_read(void)

{

	return arc_read_gfrc(NULL);

}



static struct clocksource arc_counter_gfrc = {

	.name   = "ARConnect GFRC",

	.rating = 400,
@@ -111,6 +117,8 @@ static int __init arc_cs_setup_gfrc(struct device_node *node) 
	if (ret)

		return ret;



	sched_clock_register(arc_gfrc_clock_read, 64, arc_timer_freq);



	return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);

}

TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
@@ -139,6 +147,11 @@ static u64 arc_read_rtc(struct clocksource *cs) 
	return (((u64)h) << 32) | l;

}



static notrace u64 arc_rtc_clock_read(void)

{

	return arc_read_rtc(NULL);

}



static struct clocksource arc_counter_rtc = {

	.name   = "ARCv2 RTC",

	.rating = 350,
@@ -170,6 +183,8 @@ static int __init arc_cs_setup_rtc(struct device_node *node) 


	write_aux_reg(AUX_RTC_CTRL, 1);



	sched_clock_register(arc_rtc_clock_read, 64, arc_timer_freq);



	return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);

}

TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
@@ -185,6 +200,11 @@ static u64 arc_read_timer1(struct clocksource *cs) 
	return (u64) read_aux_reg(ARC_REG_TIMER1_CNT);

}



static notrace u64 arc_timer1_clock_read(void)

{

	return arc_read_timer1(NULL);

}



static struct clocksource arc_counter_timer1 = {

	.name   = "ARC Timer1",

	.rating = 300,
@@ -209,6 +229,8 @@ static int __init arc_cs_setup_timer1(struct device_node *node) 
	write_aux_reg(ARC_REG_TIMER1_CNT, 0);

	write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);



	sched_clock_register(arc_timer1_clock_read, 32, arc_timer_freq);



	return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);

}